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[#1]

FlexSPI DDR/DTR mode support on LX2160A - DQS clarification needed

Hello,
We are working on the FlexSPI driver for the LX2160A-RDB board and have a question regarding DDR (Octal DTR) mode support.

Our board has two MT35XU512ABA flash chips connected to the FlexSPI controller. We can confirm from the board schematic that the XSPI_A_DQS signal is routed from the flash (pin C3) to the LX2160A
processor (pin E23).

However, when we attempt to use DTR mode, flash reads return invalid data (all zeroes). SDR Octal mode (1-8-8) works correctly at various frequencies.

We also noticed that in the Linux kernel, the LX2160A FlexSPI driver has FSPI_QUIRK_DISABLE_DTR set.
https://lists.infradead.org/pipermail/linux-mtd/2022-July/094127.html

Could you please clarify:

1. Does the LX2160A FlexSPI controller support DQS-based data sampling for DTR/DDR mode, or is this a known silicon limitation?
2. If DQS is not supported in silicon, what is the purpose of the XSPI_A_DQS pin routing on the RDB board?
3. Is there any configuration or errata that would allow DTR mode to function on LX2160A?

Board: LX2160A-RDB Rev B
Flash: MT35XU512ABA (*2, Octal)
Reference Manual:LX2160A Reference Design Board Reference Manual, Rev. 5, 28 September 2021

Cloud Labonline debugonline laboratoryVirtual testRe: FlexSPI DDR/DTR mode support on LX2160A - DQS clarification needed

MT35XU512ABA would have specific SPI protocol call Xccela. Not sure whether LX 2160A can support nor not

Re: FlexSPI DDR/DTR mode support on LX2160A - DQS clarification needed

Hello,

The practical answer is: treat Octal DTR on LX2160A-RDB as unsupported in Linux/LSDK unless NXP confirms a silicon revision-specific workaround. The strongest implementation evidence is the NXP Linux patch you found: it adds FSPI_QUIRK_DISABLE_DTR for LX2160A because “lx2160a do not implement DQS,” and says this causes flash probe failure in Octal DTR mode.

To your specific questions:

1. Does LX2160A FlexSPI support DQS-based DTR/DDR sampling?
   The reference manual describes the FlexSPI IP as having a DQS/read-strobe sampling mode: MCR0[RXCLKSRC] = 0x3 selects “Flash provided Read strobe and input from DQS pad,” and the input timing section explicitly describes sampling with flash-provided read strobe. However, the Linux platform data for LX2160A specifically disables DTR because the platform “do[es] not implement DQS.” So I would not rely on the generic FlexSPI IP description as proof that LX2160A silicon can use external DQS for Octal DTR.

2. Why is XSPI_A_DQS routed on LX2160A-RDB?
   The DQS pin is not only a flash-provided read strobe. The manual describes A_DQS as an I/O with multiple possible functions: external read strobe, latency information, and loopback dummy read strobe; it also notes that board-level loading on this pin can be used to compensate DATA/SCLK loading in loopback mode. The same FlexSPI block also uses DQS/RWDS as a write-mask-related signal for some write operations. Therefore, the RDB routing is consistent with the FlexSPI pin/function set and board compatibility, but it does not by itself prove that LX2160A supports external DQS-based Octal DTR reads.

3. Is there any configuration or errata that enables DTR on LX2160A?
   I found the documented configuration for DQS mode — MCR0[RXCLKSRC] = 0x3 , with DLL settings such as SLVDLYTARGET=0xF , DLLEN=1 , OVRDEN=0 when using flash-provided read strobe; for serial root clocks below 100 MHz, the manual says to use DLL override mode with OVRDEN=1 and tune OVRDVAL , with N = 18 given as a recommended value that may need adjustment. But the LX2160A-specific Linux quirk says DTR is disabled because DQS is not implemented on LX2160A, and I did not find an LX2160A erratum or documented workaround that re-enables DQS/DTR after checking the LX2160A reference manual/datasheet material, RDB reference manual material, NXP/Linux patch text, and public errata-style searches

https://lists.infradead.org/pipermail/linux-mtd/2022-July/094127.html

Recommended position for the driver: keep FSPI_QUIRK_DISABLE_DTR for LX2160A and use SDR Octal 1-8-8 . Your symptom — SDR Octal works, DTR reads return zeroes — is consistent with the upstream decision to block DTR on this SoC rather than with a simple board routing issues.

Regards