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2386781_en-US

2386781_en-US

MC33774 Balance Ctrl

HI.

I am currently using a 33665A+33774 sampling system. I encountered a problem when controlling the MC33774 equalization to start. I wanted to use the timer equalization mode and set the timeout to 10 seconds to start equalization. However, when I started equalization in the order of "MC33774_ADDR_BAL_GLOB_TO_TMR->MC33774_ADDR_BAL_TMR_CH_ALL->MC33774_ADDR_BAL_GLOB_CFG", I found that the data in MC33774_ADDR_BAL_TMR_CH_ALL was immediately cleared to 0 after being sent, causing equalization to fail to start.

Embedded_novice_0-1782462955883.png

I'd like to know what's causing this? Also, I saw in the manual that the equalization will be activated in an alternating odd and even manner. Does this mean the odd channels come first or the even channels come first? Is there a register that can control this?


Re: MC33774 Balance Ctrl

You can obtain this manual by submitting a ticket using your company email address, but you are identified as Customer C in the community because you used your own email address, so you cannot share it.

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Re: MC33774 Balance Ctrl

Thank you very much, the problem is solved. May I ask if this user manual is open source?

Re: MC33774 Balance Ctrl

Try following these steps:

guoweisun_0-1782696450136.png


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