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RT1189 - 2 octal 166MHz HyperRAMs on SPI1 to create 16-bit wide bus?

The RT1180 RM shows a Parallel FlexSPI configuration wherein two octal HyperBus memories on SPI1 to A_D7..0 and B_D7..0 to form a 16 bit wide bus.  See pages 2243 & 2244, Table 196, 6th row down which is the only entry where Effective Bus Size is listed as 16bit.  If this actually works, the max data transfer rate should be 166 MHz x 2 bytes x 2 transfers per clock period = 644 MB/s.

Has anyone tried this configuration?

If yes, does it work and what was the actual performance?

Thanks!

Re: RT1189 - 2 octal 166MHz HyperRAMs on SPI1 to create 16-bit wide bus?

Hi @DoubleD ,

Thanks for your interest in NXP MIMXRT series!

RM lists the 2×8b parallel connection mode for FLEXSPI1, but no verified RT1180 dual-HyperRAM 16-bit parallel example/benchmark was found in public resources like SDK demos or ANSW. And theoretical raw line rate is 664 MB/s, but it must not be used as guaranteed bandwidth.

This use case may require users to test it on a custom board. We apologize for any inconvenience this may cause at this stage.

Best regards,
Gavin

Re: RT1189 - 2 octal 166MHz HyperRAMs on SPI1 to create 16-bit wide bus?

Update:

The previous reply based on the description in RM. Afterward, I reconfirmed this with internal team of experts, and the conclusion is as follows:

1. FlexSPI1 supports this connection method;
2. However, performance cannot reach the theoretical upper limit. It is only about 20% to 30% faster than a single-chip HyperRAM.

Best regards,
Gavin