Hi NXP Community,
We are trying to use a particular image sensor on the i.MX8MP.
We are attempting to push the RAW12 capture from the MIPI to RAM. It seems that the only way to do this is through the ISI module as outlined below:
The problem is that the documentation on the geometry limits is vague and we are trying to determine if the i.MX8MP is suitable for our application.
The height and width of the image is defined in the ISI using the CHNL_IMG_CFG[WIDTH/HEIGHT] register. These entries are 13-bit, theoretically limiting us to 8191 x 8191 geometry.
The width seems to be limited by hardware via the line buffer which can actually only hold 2K pixels but the documentation outlines methods for reaching 4K by combining line buffers from other channels. The documentation does not cover whether the register limit of 8191 pixels for the line width can be achieved. We can bypass the ISI processing and our goal is to simply push the RAW MIPI capture to RAM.
Furthermore, unlike the width, the height limitation does not seem to be caused by physical hardware.
Is there any confirmation that we can support a height of 8191 lines as defined by the 13-bit max of the CHNL_IMG_CFG[HEIGHT] register?
Any support on the matter would be appreciated. I have reviewed other similar posts such as the following:
https://community.nxp.com/t5/i-MX-Processors/I-MX8MP-ISI-maximum-supported-width/m-p/1224069
However, whether 8191 width is supported is not confirmed and I was wondering if there are any updates here.
Also, the height limitation is not defined.
Thank you
i.mx8mp ISI driver has limited to the 2k, but if you use chain buffer, ISI can support up to 4k, couldn't support 8191 width, on the imx8mp, one camera can be supported up to 4k@30
Thank you for your reply.
So the width limitation matches my original findings.
Can you please comment on the height limitations of the ISI module? Can we achieve 8191 lane height through the ISI?
Thank you