manager:
The FS32K144UAT0VLLT circuit uses a 5VDC power supply, a 20MHz external crystal oscillator, and a 10pF matching capacitor. The external crystal oscillator does not start oscillating, and the host computer cannot connect to this chip normally using SW.
Measuring the PTA5 (RESET) level at pin 97 of this 32K144UA chip revealed a triangular wave with a frequency of 1280Hz and an amplitude of 3.3Vp-p.
As shown in the image below, please help me analyze the cause. The LDO power supply chip is working normally with 5V, so why is the crystal oscillator not oscillating? How can the reset pin generate a triangular wave? Where is the poor soldering causing this? Thank you!
Hi
The reset pin is currently connected to a capacitor, causing it to display a triangular wave. You can either remove the capacitor first and observe the reset pin waveform, or refer to section 7, " Analysis of Causes and Recovery Methods for Lockup Resets in S32K1xx Series MCUs," in the S32K1xx Se... to determine the specific situation.
The reset pin is periodically pulled low, and the program does not start running, so the crystal oscillator cannot start oscillating according to the enable bit in the program.
Do not test the chip that was previously powered by VDD 3.3V but VREFH is powered by 5V. It is recommended to resolder a chip and then use a debugger to download the program.
Best Regards,
Robin
Dear teachers:
Replenish:
The reset circuit for the FS32K144UAT0VLLT above has a 10K resistor connected to the reset pin to pull it up to +5V, and a 100nF capacitor connected to GND. Thank you!
The reset pin waveform appears to match:
② The RESET pin outputs a periodic reset pulse signal.
a. If the reset signal period is ~118µs and the high-level time is ~660ns, it is a square wave signal.
The MCU can be decrypted and recovered by executing the mass erase command through the SWD/JTAG debug interface.
I suggest using the script in the Baidu Cloud Drive link provided in this article.
manager:
After removing the capacitor from the reset circuit, it generates a pulse, as shown in the figure.
1. Referring to " 7. Analysis and Recovery Methods for Lockup of S32K1xx Series MCU Chips", J-llnk cannot connect to the computer normally, but ST-link can, but the software does not support it;
2. The reset circuit cannot connect to the J-Link properly. Does the reset circuit need to be soldered with a capacitor during connection? Currently, the reset circuit has a 10k pull-up to 5V, a 5V power supply, and a 100nF capacitor connected to GND, but it still cannot connect to the J-Link. What measures should be taken?
3. The FS32K144UAT0VLLT is new, and two have already been replaced. Why is the encryption issue occurring even with the new chip?
Thanks!
Robin_Shen:
The circuit is powered by 5V, and the reset circuit has a 10K pull-up resistor to 5V. There is no grounding capacitor. Is it necessary to add a grounding capacitor when connecting?
After entering the command "unlock kinetis" in J-Link, the computer responded as follows:
Unlocking device...ERROR: Read from DP/AP register failed!
1. The reset pin pulse waveform is shown in the figure below, with a period of approximately 118µs.
2. The entire pulse duration is 1500 ns. If the FS32K144 operates at 5V, what is the high-level reset threshold? Is the high-level duration in the diagram below 660 ns? Is the high-level duration in the diagram below acceptable?
3. Enter the command under J-Link> and take a screenshot:
(1) Enter "connect" under J-Link>, and enter "?" in the reply. Select S32K144 (ALLOW SECURITY) using FS32K144UAT0VLLT, is that correct? See the figure below:
(2) When the frequency is 112000KHZ, no suitable options appear. How should the frequency be entered here?
(3) Below are screenshots of the responses when entering commands such as Command and Unlock Kinetis in J-Link. Please check where the input is incorrect, thank you!
Either 1 or 2 is fine.
3(1) During the development phase, it is recommended not to select "allow security" (this is explained in WeChat articles, so please read them carefully).
3(2) Your chip is FS32K144UAT0VLLT, but why did you choose the S32K11 series for the Device in the screenshot? I don't understand what frequency 112000KHZ you mentioned is. You can choose a lower SWD or JTAG rate.
3(3) Didn't you say it's powered by 5V? How come VTref=3.309V? Please tell me if the debugging interface conforms to AN5426's "Table 8. S32K1xx - JTAG and SWD interface" and "Figure 11". "JTAG/SWD signal connections". Or you can send me the minimum circuit part of the schematic for me to check.
Also note that the LDO powering the S32K144 needs to provide at least 250mA (see ERR052094 for details).