Does IMG_CNTN_SET1_OFFSET secondary image boot (RM 6.1.6.2) work for ECSPI ("SPI") NOR boot on i.MX8MP, or only for FlexSPI NOR (and SD/eMMC)? Table 6-28 lists "SPI" and "FlexSPI NOR" as separate boot devices, and the secondary-offset valid values are stated only "for FlexSPI NOR boot."
Hello,
Your understanding is wrong, the IMG_CNTN_SET1_OFFSET secondary image boot also work for SPI devices, only with a different offset:
For FlexSPI = the valid values are: 0, 1, 2, 3, 4, 5, 6, and 7
For SPI = Secondary boot is disabled if fuse value is bigger than 10, n = fuse value bigger than
10.
• n == 0: Offset = 4MB
• n == 2: Offset = 1MB
• Others & n <= 10 : Offset = 1MB*2^n
Thanks — that clears up the offset mapping. Two follow-ups so we can reproduce it on our i.MX8MP board (boot NOR on ECSPI2, OPEN / non-HAB config, fuse read 2 1 = 0 → n=0 → 4 MB):
What triggers the ROM to switch to the secondary image on SPI NOR? Is it any invalid primary boot header / failed image parse, or specifically a HAB authentication failure? In other words, does secondary-image boot work in open (non-secured) configuration, or only when the device is HAB-closed?
Does it fall back on the same reset, or does it require a power cycle / a second reset (persistent-boot style)?
Must the secondary image at the 4 MB offset be a separately-built bootable image (its own IVT/boot data for that offset), or is a byte-identical copy of the primary sufficient?
On i.MX8MP booting from ECSPI (SPI) NOR in the OPEN (SEC_CONFIG=open, non-HAB) configuration: what is the exact trigger condition for the IMG_CNTN_SET1_OFFSET secondary image boot? Does the ROM switch to the secondary image on an invalid/erased primary container header, or only on a HAB authentication failure (i.e. only in the closed/secured configuration)? We have a valid secondary copy at 4MB (fuse n=0), erased the primary header, and the ROM does not fall back in open config.