2383578_en-US

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High Drive Strength on S32K3

The S32K3XX reference manual talks about the "drive-strength enable" bits, but doesn't appear to define what this means - the closest reference I can find is that it seems correlated with maximum frequency supported by certain pins (page 42 of the S32K3XXRM/Section 4.4.1)

Is there something explicit in terms of maximum current draw or other things I should be aware of for why I should or should not enable "drive-strength"?

Re: High Drive Strength on S32K3

GPIO-Standard: Switching up to 10 MHz High drive-strength not supported. Slew-rate control not supported.
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GPIO-Standard plus: Switching up to 25 MHz  Supports high drive-strength. Slew-rate control not supported.
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GPIO-Medium: Switching up to 50 MHz  Supports high drive-strength. Supports slew-rate control.
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GPIO-Fast: Switching up to 120 MHz Supports high drive-strength. Supports slew-rate control.

Re: High Drive Strength on S32K3Yes, that is exactly the text of the section I cited in my question. That doesn't tell me why I should or shouldn't enable "drive strength" - it just tells me that some pins support it, and that some switching rates are related to it.

If I were driving an LED with it, would it be capable of sinking more current? How much more current?

Is it purely a slew-rate change?

Is there a reason not to enable it, if the pin supports it? Will my chip dissipate more heat if I enable it?Re: High Drive Strength on S32K3

Hardware Design Guidelines for S32K39x, S32K37x and S32K36x Microcontrollers