2383549_en-US

[#1]

i.MXRT1176: Question about accessing an external SRAM

Hello,

I'm having trouble accessing an external SRAM. The SRAM is selected via CSX1 (Pad L14 – GPIO_AD_26), and my test program always triggers a MemoryManage Fault. What mistake did I make in my code? Thank you in advance for your help.

/*

* Copyright 2017 NXP

* All rights reserved.

*

* SPDX-License-Identifier: BSD-3-Clause

*/

#include "board.h"

#include "fsl_debug_console.h"

#include "fsl_device_registers.h"

#include "pin_mux.h"

#include "fsl_semc.h"

#include "clock_config.h"

/*******************************************************************************

* Definitions

******************************************************************************/

#define EXAMPLE_SEMC SEMC

#define EXAMPLE_SEMC_CLK_FREQ CLOCK_GetRootClockFreq(kCLOCK_Root_Semc)

/*******************************************************************************

* Prototypes

******************************************************************************/

extern status_t BOARD_InitSRAM(void);

/*******************************************************************************

* Variables

******************************************************************************/

/*******************************************************************************

* Code

******************************************************************************/

#define SRAM_BASE 0x60000000

//#define SRAM_BASE 0x81000000

status_t BOARD_InitAsyncSRAM_CS1(void)

{

semc_config_t config;

semc_sram_config_t xsram_config;

uint32_t clockFrq = kCLOCK_Root_Semc;

SEMC_GetDefaultConfig(&config);

config.dqsMode = kSEMC_Loopbackdqspad;

SEMC_Init(SEMC, &config);

memset(&config, 0, sizeof(semc_config_t));

memset(&xsram_config, 0, sizeof(semc_sram_config_t));

xsram_config.address = 0x60000000;

xsram_config.memsize_kbytes = 512;

xsram_config.addrPortWidth = 16;

xsram_config.portSize = kSEMC_PortSize16Bit;

xsram_config.addrMode = kSEMC_AddrDataNonMux;

xsram_config.syncMode = kSEMC_AsyncMode;

xsram_config.advActivePolarity = kSEMC_AdvActiveLow;

xsram_config.advLevelCtrl = kSEMC_AdvLow;

xsram_config.burstLen = kSEMC_Nor_BurstLen1;

xsram_config.tWeLow_Ns = 25;

xsram_config.tWeHigh_Ns = 25;

xsram_config.tReLow_Ns = 25;

xsram_config.tReHigh_Ns = 25;

xsram_config.tTurnAround_Ns = 10;

xsram_config.cePinMux = kSEMC_MUXCSX1;

xsram_config.waitEnable = true;

xsram_config.waitSample = true;

xsram_config.tCeSetup_Ns = 25;

xsram_config.tCeHold_Ns = 20;

xsram_config.tAddrSetup_Ns = 25;

xsram_config.tAddrHold_Ns = 25;

xsram_config.tWriteSetup_Ns = 25;

xsram_config.tWriteHold_Ns = 25;

xsram_config.readCycle = 30;

xsram_config.readHoldTime_Ns = 25;

xsram_config.tCeInterval_Ns = 25;

xsram_config.tAddr2WriteHold_Ns = 25;

xsram_config.latencyCount = 3;

xsram_config.delayChain = 25;

xsram_config.addr27 = kSEMC_MORA27_NONE;

SEMC->IOCR |= 0x00908BB6;

// SEMC->IOCR |= 0x08;

return SEMC_ConfigureSRAMWithChipSelection(SEMC, kSEMC_SRAM_CS1, &xsram_config, clockFrq);

}

/*!

* @brief Main function

*/

int main(void)

{

/* Hardware initialize. */

BOARD_ConfigMPU();

BOARD_InitPins();

BOARD_BootClockRUN();

BOARD_InitDebugConsole();

BOARD_InitAsyncSRAM_CS1();

SEMC->IOCR |= SEMC_IOCR_MUX_CSX1(0x08);

PRINTF("\r\n Start SEMC SRAM MSpec with WAIT write test.\r\n");

PRINTF("CCM_OBS_SEMC_CLK_ROOT： %d\r\n", CLOCK_GetFreqFromObs(CCM_OBS_SEMC_CLK_ROOT));

//////////////////////////////////////////////////////////////////////////////////////////////

volatile uint16_t *sram_ptr = (volatile uint16_t *)0x60000000;

uint16_t i = 0;

*sram_ptr = 0;

for (i = 0; i <= 10; i++)

{

*sram_ptr = i;

}

for (i = 0; i <= 10; i++)

{

PRINTF("\r\n sram = %d \r\n", sram_ptr);

}

}