I am using the RT1160 with external 16-bit SDRAM and 16-bit SRAM(for fpga communication). The SRAM interface is configure as SRAM Read/Write Operation in ASYNC Mode with Wait Pin. I wonder If the wait signal will conflic with SDRAM refresh timing to cause some issue. We've test it to let our code in SDRAM and let wait pin keep low about 10ms or longer in SRAM ASYNC write, sometimes it will end at about just 1ms and don'tknow why.
can we use in that way or ther have some limitation when using both SDRAM and SRAM device. Thanks for your help.
Hi
What are you referring to when you mention that it will end at about 1 ms? Does the SRAM write return an error, or does it enter a hard fault? How often does this happen?
Could you please help me test the following?
1. Run the code from internal memory (not SDRAM) and repeat the long asynchronous SRAM write.
2. While still executing the code from internal memory, run the same test again, but this time with SDRAM enabled but idle.
3. Run the test as you originally mentioned, but with the SRAM wait signal held active.
Additionally, could you check the following during these tests (including the ones mentioned above)
Could you monitor the SRAM signals during the transfer?
Could you share the SEMC INTR register values for each test?
Please let me know your results.
Best Regards,
Pablo