2382563_en-US

是

LA9310 LLCP external interface signal description and AC timing table,

Trying to interface ADRV9002 with LA9310. Needs LA9310 LLCP external interface signal description and AC timing table,

LA9310 material does not provide enough detail to map:

LLCP lane count
exact serial word format
I/Q bit ordering
whether ADC/DAC samples are raw streams or encapsulated transactions

OR

Can we bypass or power down ADC and DAC.
or

how can we configure LA9310 interface with SSI LVDS compatible with ADRV9002

Re: LA9310 LLCP external interface signal description and AC timing table,

Hello,

No, the available LA9310 documentation does not provide enough information to directly map ADRV9002 SSI/LVDS onto the LA9310 LLCP interface. LA9310 documents do define the LLCP pins, link style, transaction types, and electrical/timing characteristics, and they also show that the internal ADC/DAC can be put into low-power modes. But I could not find documentation that specifies the LLCP details you asked for at the level needed for an ADRV9002 interoperability design: lane count beyond the single data+strobe pair per direction, exact end-to-end serial sample word format for I/Q streaming, explicit I/Q bit ordering on the LLCP pins, or any statement that LLCP is SSI-compatible

Regards

Re: LA9310 LLCP external interface signal description and AC timing table,

Thanks,

further if you can recommend any compatible zero IF or near zero IF RFIC for frequency 240 to 360MHz. . I am exploring LMS7002 but it becomes less useful without TSP. Or if you recommend without TSP then can I use LA9310 .

With LMS7002 internal TSP you normally get:

Digital upconversion/downconversion
Interpolation/decimation filtering
IQ correction
DC offset correction
Some gain control functions
Digital frequency shifting
Digital waveform shaping

or

I found CMX998 if other stuff as above mentioned possible inside LA9310 to achieve BPSK/QPSK/8PSK for low bandwidth channels like 5KHz and 25KHz for tx rx data rate 2.4 KB/s to 64KB/s only.