2382486_en-US

[#1]

SPI (Slave) + DMA data reception error

When the S32K144 SPI is configured in SLAVE mode and uses DMA, data misalignment occurs during data reception (e.g., the correct sequence should be 1, 2, 3, 4, 5, 6, but the actual received data is 3, 4, 5, 6, 1, 2, indicating a misalignment). Analysis of the communication data sequence using an oscilloscope shows it is normal, and the data received by the SPI during the first communication is also normal. The current communication method is that the master and slave microcontrollers periodically trigger SPI communication.

Re: SPI(Slave )+DMA 数据接收异常

IDE:S32 Design Studio for ARM Version 2.2, custom board.

Re: SPI(Slave )+DMA 数据接收异常

Hi @GLB 

Which software and IDE you are using? Could you please share your code and configuration so I can try to reproduce the issue on my side?

Also, are you working with a custom board or an evaluation board (EVB)?

BR, VaneB

Re: SPI(Slave )+DMA 数据接收异常

Hi @GLB 

A possible reason for the observed receive data misalignment could be an incomplete synchronization between the LPSPI RX FIFO state and the DMA RX TCD state before starting a new transaction.

The first received frame sequence is correct, but subsequent transfers could become shifted if the RX FIFO still contains pending data. You can try disabling DMA requests, clean the LPSPI FIFOs, clearing SPI and DMA status flags, and reloading the RX/TX DMA TCDs before initiating a new transfer. A similar approach is implemented in the Thread SPI slave DMA chip select restart; although it is not specific to the S32K144 device, it can serve as a useful reference.

Additionally, the S32K1 SDK example lpspi_dma_s32k144 can also be used as a reference.

Re: SPI(Slave )+DMA 数据接收异常

Hi @GLB 

Timing variations can still lead to some misalignment. It could work well as long as both sides stay tightly synchronized.

Re: SPI(Slave )+DMA 数据接收异常

The master sends data at a 10ms cycle, and the slave also triggers DMA to move data at a 10ms cycle. Is this communication method reasonable? Even if the FIFO is cleared before the slave DMA moves data, data misalignment is still possible, right?

Re: SPI(Slave )+DMA 数据接收异常

I checked the S32K144 manual and found that the SPI only has receive and transmit interrupts, not chip select interrupts, and the DMA only has a transfer completion interrupt. I tried configuring the SPI receive interrupt, but the misalignment still occurs. It seems that SPI itself cannot solve this problem. I think an additional synchronization signal needs to be added between the master and slave to ensure the correctness of the SPI. Do you have any other suggestions? Thank you.