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GD3160 SPI 配置

According to the data sheet, if I want to configure the GD3160, I need to first set the CONFIG_EN bit in MODE_2 to 1. In that case, should the first bit of MODE_2, Rb/W, be 0 or 1?

Re: GD3160 SPI 配置

了解了请看下面:

The correct interpretation is indeed:
0 = Read
1 = Write

 
Re: GD3160 SPI 配置

Yes, and in addition to the CONFIG1 through 7 registers, the MODE1 and 2 registers, the RMSK1 and RMSK2 registers, and the MSK1 and 2 registers shown in the figure below—writing to these registers is controlled by CONFIG_EN in MODE_2—will the remaining registers be configured whenever bit 23 is set to 1?

henh_0-1781578575329.pnghenh_0-1781578575329.png



Re: GD3160 SPI 配置

guoweisun_0-1781578136768.pngguoweisun_0-1781578136768.png

Are you talking about bit23?


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最后更新:
‎06-17-2026 03:26 AM
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