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Hello,
We are trying to generate a Challenge-Response value for Secure Debug on S32N55 using the following script from the T32 demo folder:
C:\T32_S32N55\demo\arm\hardware\s32n55\s32n55-evb\s32n55-evb-fss\s32n55-evb_sieve_sram_challenge_response_smartcard.cmm
&UID0=FORMAT.HEX(16.,CHIP.SecureChallenge(0))
&UID1=FORMAT.HEX(16.,CHIP.SecureChallenge(1))
&CHAL0=FORMAT.HEX(8.,CHIP.SecureChallenge(2)&0xFFFFFFFF)
Current status:
ADKP injection: completed successfully
Lifecycle transition to HSE_LC_OEM_CLOSED: completed
However, Device Unlock Fail still occurs
Questions:
Are there any additional prerequisites for 256-bit Challenge-Response (C/R) Secure Debug on S32N55 beyond ADKP injection and LC transition to OEM_CLOSED?
On S32K3, the Challenge value can be retrieved directly via SDAP registers as shown below. Is there a similar register-based approach for S32N55?
&SDAP_BASE_ADDRESS=0x40000700
&SDAP_AUTHSTTS = &SDAP_BASE_ADDRESS
&SDAP_AUTHCTL = &SDAP_BASE_ADDRESS+0x4
&SDAP_KEYCHAL_0 = &SDAP_BASE_ADDRESS+0x10
&SDAP_KEYCHAL_1 = &SDAP_BASE_ADDRESS+0x14
&SDAP_KEYCHAL_2 = &SDAP_BASE_ADDRESS+0x18
&SDAP_KEYCHAL_3 = &SDAP_BASE_ADDRESS+0x1C
&SDAP_KEYCHAL_4 = &SDAP_BASE_ADDRESS+0x20
&SDAP_KEYCHAL_5 = &SDAP_BASE_ADDRESS+0x24
&SDAP_KEYCHAL_6 = &SDAP_BASE_ADDRESS+0x28
&SDAP_KEYCHAL_7 = &SDAP_BASE_ADDRESS+0x2C
Is CHIP.SecureChallenge(2) the correct command for S32N55 256-bit Challenge, or is a different T32 command required?
We have a project deadline of June 19th and would greatly appreciate your prompt response.
Any guidance would be greatly appreciated.
Hello, @EddiePark
Additionally, be aware that before using the script to unlock the debug port, it is needed to register the ADKP into volcano database.
For details, you could get more details from C:\T32\demo\tools\nxp\sdaf\user_guide.pdf
BR
Chenyin
Hello, @EddiePark
Thanks for your post.
1. I understand your status, and has queried corresponding team for locating your questions, it may take some time and I will try my best to help.
May I know if your testing setup is still based on the following setup?
- Platform: S32N55 EVB
- HSE FW Version: HSE_FW_S32N5_1_0_24_0
- GrayVIP Version: SW32N5_GRAYVIP_1_0_22_0
2. The S32K3 uses HSE1 and the S32N55 uses HSE2, so the process might not be translatable, I don't know the details on how the S32K3 challenge-response works, however, as far as I know, HSE2 has a very different architecture.
3. I feel sorry that as what I ever mentioned in your previous post, since S32N55 is still in pre-production phase, there would be limited support for the community post according to our rule.
4. I understand that it is urgent for your case, if it is possible, it would be more efficient to contact your distributor/NXP representative, to obtain direct support from them for questions on such a pre-production silicon.
BR
Chenyin