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T1042 DDR4 DQ MAP Register Settings

We are about to receive a new design using the T1042 processor with DDR4.  We had to swap bits within the byte lanes to optimize the DDR4 routing.  I am aware that there is a set of DQ MAP registers which need to be utilized to account for the bit swapping.  However the instructions in the reference manual for setting the bits in these registers is unclear.

We had another instance of the DQ MAP settings at our site which was working successfully, however the settings they were told to use via NXP on this forum do not match what I would expect based on what the reference manual says.  My colleague's post is this one:  Re: T1042 DDR4 failed to initialize - What to look at - NXP Community

There are cases within the older working design DQ MAP settings where the value is 1 off from what my interpretation of the reference manual would dictate.  Would someone at NXP be able to help review the settings I came up with for my design and ensure they are correct so we have the best chance of success at bringing up the DDR4?  My expected settings and schematic snippets of the mapping are attached.

QorIQ T1 DevicesRe: T1042 DDR4 DQ MAP Register SettingsThank you for the reply and verification. I forgot to include the ECC screenshot however we did not do any swapping within the ECC byte. I greatly appreciate your support.Re: T1042 DDR4 DQ MAP Register Settings

Could not find ECC lines, but others are correct.

Thanks.