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S32K3X8EVB-Q289 Boundary Scan test based on Lauterbach μTrace and Trace32.

1. Abstract/Introduction

Boundary scan is a method for testing interconnects (wire lines) on printed circuit boards or sub-blocks inside an integrated circuit (IC). Boundary scan is also widely used as a debugging method to watch integrated circuit pin states, measure voltage, or analyze sub-blocks inside an integrated circuit.

The Joint Test Action Group (JTAG) developed a specification for boundary scan testing that was standardized in 1990 as the IEEE Std. 1149.1-1990. In 1994, a supplement that contains a description of the boundary scan description language (BSDL) was added which describes the boundary-scan logic content of IEEE Std 1149.1 compliant devices. Since then, this standard has been adopted by electronic device companies all over the world. Boundary scan is now mostly synonymous with JTAG.

This test is based on existing application notes for LPC55(S)xx, i.MX RT and MCXA (See references).

The procedure follows how to do both a BYPASS, IDCODE and SAMPLE test, as well as an EXTEST. Following boundary scan instructions are defined in the IEEE standard:

• BYPASS (mandatory): TDI is connected to TDO via a single shift register.
• IDCODE (optional): Reads the device identification register.
• SAMPLE (mandatory): Takes a snapshot of the normal operation of the IC.
• EXTEST (mandatory): Apply preloaded data of the boundary scan register to the ports.

2. Hardware platform

Lauterbach: LA-3505 POWER-DEBUG-PRO
S32K3: S32K3X8EVB-Q289

There are no hardware modifications needed for connecting JTAG interface, as the S32K3 family includes the standard Arm debug port, supporting both the JTAG and SWD interfaces. S32K3XX derivatives can directly use the JTAG interface.

Ensure S32K3X8EVB-Q289's jumpers are set as in the Quick Start Guide for S32K3X8EVB Board:

Default Jumper settings.Default Jumper settings.

Ensure a valid connection between the EVB's JTAG ARM 20-pin Standard Port (On board: J365), and the Debug Cable for Lauterbach interface.

3. Software platform

This test uses Lauterbach's TRACE32 Software Package.

Download the TRACE32_202509.7z to the computer and install it:

1. Because the installation package is relatively large, you can install software components according to the target processor to save hard disk space.
2. You can find installed driver at C:\T32\bin\windows64\drivers.

4. BSDL file validation using Lauterbach JTAG debugger.

1. Confirm that Lauterbach probe is detected in 'Device Manager':
   Device Manager Trace32 device enumeration.Device Manager Trace32 device enumeration.
   

   
   Note: Lauterbach debugger used is LA-3500, with Probe LA-3000 + LA-7844A Debug License. Related information can be found on the Lauterbach's page.

2. Open TRACE32 Arm interface:
   
   
   
   
3. Type in the following commands:
   

   SYStem.Down		
   BSDL.RESet		
   BSDL.ParkState Select-DR-Scan	
   BSDL.state		

   
   
4.  BSDL.state window should now appear. Select 'FILE' and load BSDL from S32K3 HW Design Package.
   
   S32K3X8EVB-Q289 should use S32K358_bga289_customer_1995E01D.bsdl.
   
   BSDL.state window.BSDL.state window.
   
   
5.  After loading the file, type the following command:
   

   BSDL.SOFTRESET​

6. Switch to the Check tab of the BSDL.state window. Click BYPASSall and IDCODEall button to see if both results pass. Both should change from 'No result' to 'Test PASS':
   BYPASS and IDCODE check.BYPASS and IDCODE check.

   BYPASS: PASS means the bypass scan completed correctly for all configured devices. This indicates that the JTAG chain connectivity, chain order/length, and basic BSDL configuration are probably correct.
   
   IDCODE: PASS means the received device ID matches the expected BSDL description. This is evidence that the correct device and BSDL file are being used, but it still does not validate the boundary-register pin definitions.

7. Next, click the SAMPLEall button, 'No result' should become Test done. Double-click the entity name, and the BSDL.SET window will pop-up:
   
   BYPASS and IDCODE check, BSDL.SET window appears.BYPASS and IDCODE check, BSDL.SET window appears.
   
   SAMPLE: PASS indicates that the pin can be observed through the boundary-scan cell, the BSDL input/observe mapping is likely correct, and that the captured value corresponds to the actual pad level.
   
   
8. In the BSDL.SET window, uncheck Intern option to filter out the internal registers. The remaining contents are the sampled value on each signal pins. Use a multimeter to measure voltage of at least three signal pins and see if the logic state matches the sampled value.
   
   BSDL.SET window, SAMPLE check.BSDL.SET window, SAMPLE check.
   
9. Next, in the Instructions field, click EXTEST and in the DR mode field, choose Set Write. Then switch to the BSDL.state window and check SetAndRun and TwoStepDR.
   
   BSDL.SET & BSDL.STATE windows EXTEST set up.BSDL.SET & BSDL.STATE windows EXTEST set up.
   
10. Switch back to BSDL.SET window, click 'ENABLE' in Init BSR to enable output of corresponding signal pins, and click the buttons in “Reg.” column to toggle their output logic state 0 or 1. Use a multimeter to measure if the logic state really toggles on those signal pins. At least three signal pins need to be verified.
    
    BSDL.SET window enable and toggle signal levelBSDL.SET window enable and toggle signal level

    
    Note: PTG29/30/31 (User LED indicators Red/Green/Blue) for simplicity reasons, however, as a diagnostic recommendation, use an unloaded or lightly loaded pad if possible.

5. Conclusion

This procedure provides a practical method for validating the S32K3X8EVB JTAG boundary-scan chain using TRACE32 and the appropriate S32K358 BSDL file. BYPASSall and IDCODEall verify JTAG-chain connectivity and device identification, SAMPLEall confirms pin-state observation, and EXTEST verifies pin control through the boundary-scan register.

While these checks confirm basic boundary-scan operation, additional pin-level testing is recommended to validate board connectivity and application-specific signals. Any reset observed during EXTEST should be investigated before concluding a BSDL-related issue.

The final report should capture the BSDL file used, JTAG-chain results, validated pins, measured logic levels, and any reset behavior observed during EXTEST.

6. References

• How to Perform Boundary Scan for LPC55(S)xx based on μTrace
• AN12919: Introduction to Boundary Scan of i.MX RT Series – Application Note
• How To Perform Boundary Scan On MCXA Series Using μTrace And Trace32
• Boundary Scan User's Guide
• S32K3 Auto General-Purpose MCUs | NXP Semiconductors
• Software Download | Lauterbach TRACE32