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[#1]

Unable to measure 1PPS signal on J12 pin of LS1028A evaluation board？

After booting the development board, I enabled PPS output using the command echo 1 > /sys/class/ptp/ptp0/pps_enable. Then, by running cat /sys/class/pps/pps0/assert, I can see the timestamp incrementing. However, I cannot capture the PPS signal on the 1588_PULSE_OUT2 pin.

I searched for similar issues in the forum and then modified the device tree by referring to the devicetree/bindings/ptp/ptp-qoriq.txt document. The steps are as follows:

First, I obtained the clock value for QORIQ_CLK_HWACCEL 3 on the board using the following command. The value is 400 MHz:

root@ls1028ardb:# find /sys/kernel/debug/clk -name "clk_summary" -exec cat {} ; | grep -i hwaccel
cg-hwaccel3 0 0 0 400000000 0 0 50000 Y deviceless no_connection_id
cg-hwaccel0 0 0 0 400000000 0 0 50000 Y deviceless no_connection_id
cg-hwaccel2 0 0 0 600000000 0 0 50000 Y f200000.display clk_core
cg-hwaccel1 0 0 0 1200000000 0 0 50000 Y deviceless no_connection_id

So I modified the device tree file fsl-ls1028a.dtsi as follows:

ethernet@0,4 {
    compatible = "pci1957,ee02", "fsl,enetc-ptp";
    reg = <0x000400 0 0 0 0>;
    clocks = <&clockgen QORIQ_CLK_HWACCEL 3>;
    little-endian;
    fsl,extts-fifo;
    // The following lines are newly added
    fsl,cksel = <1>;
    fsl,tclk-period = <10>;
    fsl,tmr-prsc = <100>;
    fsl,tmr-add = <0x40000000>;
    fsl,tmr-fiper1  = <0x3B9AC9F6>;
    fsl,max-adj = <2999999999>;
};

After booting, the modified node entries are visible:

root@ls1028ardb:~# ls /sys/class/ptp/ptp0/device/of_node/
clocks  compatible  fsl,cksel  fsl,extts-fifo  fsl,max-adj  fsl,tclk-period  fsl,tmr-add  fsl,tmr-fiper1  fsl,tmr-prsc  little-endian  name  reg

Even after these modifications, I still cannot capture the signal correctly. Therefore, I checked the RCW values. The detailed log is as follows:

Reset Configuration Word (RCW):
       00000000: 3c004010 00000030 00000000 00000000
       00000010: 00000000 018f0000 0030c000 00000000
       00000020: 020031a0 00002580 00000000 00003296
       00000030: 00000000 00000010 00000000 00000000
       00000040: 00000000 00000000 00000000 00000000
       00000050: 00000000 00000000 00000000 00000000
       00000060: 00000000 00000000 200e705a 00000000
       00000070: bb580000 00000000

In the LS1028ARDBRM.pdf document, I found that for 1PPS output, the EC1_SAI4_5_PMUX[835:833] field must be set to 101. The word address is the 32-bit word at offset 0x68 (word 26), with value 0x200e705a. Extracting this field: shift right by 1 and mask lower 3 bits: (0x200e705a >> 1) & 0x7 = 0x5, which is binary 101 – so that is also correct. However, I still cannot capture the signal.

I would like to know whether my device tree configuration is incorrect, or if there might be other hardware limitations. I have attached the ptp-qoriq.txt, LS1028ARDBRM.pdf, and the oscilloscope capture for reference.

Re: Unable to measure 1PPS signal on J12 pin of LS1028A evaluation board？

I performed a loopback test with the following commands and got no signal. It is indeed possible that the CPLD is not routing the signal correctly.

root@ls1028ardb:~# find /sys/kernel/debug/ -name fiper1-loopback          
/sys/kernel/debug/0000:00:00.4/fiper1-loopback
root@ls1028ardb:~# echo 1 > /sys/kernel/debug/0000:00:00.4/fiper1-loopback
root@ls1028ardb:~# cat /sys/class/ptp/ptp0/fifo                           
root@ls1028ardb:~# cat /sys/class/ptp/ptp0/fifo
root@ls1028ardb:~# cat /sys/class/ptp/ptp0/fifo

The CPLD software version I am using is LS1028ARDB_HDL_2020_0330_1829_V8. Is additional programming required? Or is there an issue with this version? As for the routing problem, I will have our hardware team check it.

Re: Unable to measure 1PPS signal on J12 pin of LS1028A evaluation board？

Hello,

The documentation supports that LS1028A can output PPS on LS1028ARDB J12, but your symptom most likely points to missing board RCW/CPLD mux routing or incomplete external FIPER pin programming rather than a lack of PPS support.

Regards