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i.MX RT1176 - Dual-core XIP and CM4 code execution from SDRAM

Dear NXP Support Team,

We are working with the i.MX RT1176 processor and plan to use both the CM7 and CM4 cores. Both program images will be stored in a single QSPI flash connected via FlexSPI1.

We have two questions:

1. Dual-core XIP
We would like to know whether both CM7 and CM4 can perform XIP (Execute in Place) operation simultaneously from the same QSPI flash.
- Is simultaneous dual-core XIP from a single Flex SPI flash supported on the RT1176?
- Are there any performance or bus arbitration considerations when both cores fetch instructions from the same flash interface concurrently?
- Are there any NXP SDK examples or application notes demonstrating this configuration?

2. CM4 code execution from SDRAM
We have seen that most examples load the CM4 image into ITCM RAM for execution. However, we are planning to run heavier tasks on CM4 and may need more code space than what ITCM offers. Can the CM4 core execute code from SDRAM (via SEMC) instead of ITCM? If so, are there any examples or application notes covering this approach?

Any guidance would be appreciated.

Best regards,

Calixto Systems Pvt Ltd

Re: i.MX RT1176 - Dual-core XIP and CM4 code execution from SDRAM

Hi NXP Support,

Just following up to see if there are any updates or guidance regarding these questions?

Thank you!

Re: i.MX RT1176 - Dual-core XIP and CM4 code execution from SDRAM

Hi @sanjana291,

1. Yes, both CM7 and CM4 can perform XIP operation from the same QSPI flash. The FlexSPI controller that communicates with the QSPI flash is connected to the AXI/AHB bus matrix, which handles both cores as bus masters, but arbitrates access to ensure both can fetch instructions without mix-ups. With respect to performance or arbitration considerations, there aren't any specific issues since the bus matrix handles the transactions effectively. The best performance would still be having two instances of FlexSPI, connecting each core to a different flash device.

2. Yes, the CM4 can execute code from SDRAM (via SEMC) instead of ITCM by adjusting the linker file configuration. 

For both cases, although possible, we do not have example projects demonstrating these setups, since generally they aren't the conventional or most efficient configurations, so the actual implementation would have to be done manually.

BR,
Edwin.