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i.MX93 LPSPI7 Usage on Cortex-M33 and Sampling Rate Verification

Hi NXP Team,

I would like to ask whether LPSPI7 on the i.MX93 can be assigned to and controlled by the Cortex-M33 core instead of the Cortex-A55 cores.

If this is supported,
Is there any reference example or SDK project demonstrating LPSPI7 operation on the M33 core?

In addition, I would like to evaluate the SPI performance when running on the M33 core.

Is there a recommended method to measure the actual SPI sampling rate / data throughput?
Are there any known limitations regarding the maximum achievable SPI clock frequency or sampling performance when LPSPI7 is controlled by the M33 core?

Thank you.

BR,

Sean

LinuxRe: i.MX93 LPSPI7 Usage on Cortex-M33 and Sampling Rate Verification

1. Can LPSPI7 be assigned to Cortex‑M33 instead of Cortex‑A55?

Yes.

Practical configuration steps (inferred from architecture)

You will need:

1. TRDC configuration
• Assign LPSPI7 peripheral region to M33 domain
• Remove A55 access (optional but recommended for isolation)
2. Clock + reset setup
• Typically done by A55 → passed to M33 (or handled via SCFW/firmware depending on flow)
3. Interrupt routing
• Ensure LPSPI7 IRQ enabled in M33 NVIC
4. DMA (optional)
• Use eDMA channel:
• TX: mux slot 83
• RX: mux slot 84

2. Is there an SDK example for LPSPI on M33 (i.MX93)?

What likely exists (based on MCUXpresso design)

• Generic LPSPI driver for Cortex‑M33
• Example projects (board-dependent):
• lpspi_master
• lpspi_interrupt
• lpspi_edma

3. How to measure SPI throughput / sampling rate?

Method 1 — GPIO toggle (cycle-accurate)

Method 2 — pure bus clock verification

Method 3 — DMA stress test (recommended)

For max throughput:

• Use LPSPI + eDMA
• Continuous transfer (loop / ping‑pong buffer)
• Measure:
• sustained bandwidth
• CPU utilization

4. Performance / clock limitations on M33

The RM provides system capability but does not explicitly state “M33-specific SPI limit”.

However:

• M33 runs @ ~250 MHz
• LPSPI supports DMA (important for high throughput)
• No architectural limitation tying SPI speed to A55

Re: i.MX93 LPSPI7 Usage on Cortex-M33 and Sampling Rate Verification

I discussed more with the AE team, please refer to the following update from them.

i.MX93 does not isolate M33 and A55 cores. LPSPI7 can be controlled by M33 without any changes, the bottom line is you don't control it from A55 side simutaniously.

There's no specific SDK example for LPSPI7. You'll have to adapt to LPSPI7 using existing examples.

To measure the actual SPI sample rate, an oscilloscope or logic analyser is recommended. M33 should be able to reach the max data rate specified in the specs, no known limitations as I'm aware of.

Re: i.MX93 LPSPI7 Usage on Cortex-M33 and Sampling Rate Verification

Hi @yipingwang ,

Thank you for your reply.

Could you also confirm whether both TPM2 and ADC1 can be controlled by the M33 core?

We noticed a statement in the i.MX93 Reference Manual indicating that "any peripheral can be assigned to any domain." Based on this, it appears that TPM2 and ADC1 should be assignable to the M33 domain. However, we would like to double-check and obtain confirmation from NXP.

Thank you!

Best Regards,

Sean

Re: i.MX93 LPSPI7 Usage on Cortex-M33 and Sampling Rate Verification

Yes, there's no restriction to assign TPM2 and ADC1 to M33

Re: i.MX93 LPSPI7 Usage on Cortex-M33 and Sampling Rate Verification

Hi @yipingwang ,

OK, thank you