We are working on an i.MX937 based automotive cluster design and had a few architecture questions:
1) We are currently a hardware platform based on i.MX937 and need to finalize the buck regulator selection. We have review schematics, as per our application requirement, we need only single output.
Our project requirements are follows
7'' LVDS touch screen display, wireless module, LPDDR5 & eMMC ( same IC as used in EVK) ,MFI chip, GNSS Module, USB, other communication device
Additional we required CPU,NPU power sequence, Power consumption if possible calculation sheet/documents. In the EVK schematic, the maximum current mentioned for VDD_SOC is 12A. We would like to understand whether such high current capability required for our application use case.
2) In which case is there a need for two PMICs instead of a single PMIC?Is it mainly due to additional power rail/current requirement.
3) I also noticed some design use an additional AND gate on the watchdog path instead of directly connecting the watchdog output to reset . Under what condition is this extra logic is required ?
i.MX937 is still in pre production information is very restricted and limited
Please contact your local NXP support for further details they will provide you the information you request.
B.R
Currently, I am working on the i.MX937 based project, so I wanted to confirm whether the same VDD_SoC current and power rail design consideration applicable for i.MX937 as well, or if there separate hardware design guide document.
Also could you please share the maximum current requirement details for i.MX937 core rails?
The maximum VDD_SOC current is 2700mA. Not 12A. And about HW design, please refer the IMX93HDG.
B.R
Hello NXP team,
Regarding the i.MX937, please clarify whether the 5.8W specification indicates the total SoC power dissipation or exclusively the core rail power.
