2366928_en-US

[#1]

LA1224 LS-DCS & TBGen

Hello!
Could you tell me how to enable continuous synchronous operation of 4T4R on the LA1224-RDB-LS?
I'm using 0-3 VSPA cores to run LS-DCS0 and LS-DCS1.
1DAC and 1ADC are running on each core.
I have interrupt handlers for TBGEN, and I configured TBGEN in FDD mode. But I'm not receiving interrupts from it on the VSPA.
I was able to run 2T2R synchronously, but in this case, either the ADC or DAC is running on each core.
Perhaps I haven't configured all the TBGEn timers?
I'm transmitting a single-tone signal generated using NCO with 8192 samples. I'm sure I generated the NCO parameters correctly.
But why do I see phase jumps on the ADC during loopback?

Re: LA1224 LS-DCS & TBGen

Yes, you're right, I wasn't entirely correct. It's the ext_go timers that aren't reaching VSPA. It's probably necessary to enable the TimedCTRL_0 - TimedCTRL_11 timers. Right now, I've only initialized TDD0_CTRL - TDD7_CTRL; see my dump. I don't understand how to set TimedINTRVL0 - TimedINTRVL11 correctly.

Re: LA1224 LS-DCS & TBGen

Hello,

The key point is that TBGEN timed-interrupt timers 1–11 are VSPA trigger sources, not VSPA interrupt sources . Only Timed Interrupt Timer 0 can generate an MCU interrupt through INTSTAT[TI] and CNTRL1[TIIE] ; timers 1–11 only generate VSP platform triggers and set TISTAT[TITRIG1..11] . So if you configured TBGEN in FDD mode and are waiting for a TBGEN “interrupt” on a VSPA core, that expectation does not match with TBGEN/VSPA interface.

For LA1224 4T4R, TBGEN timers 1–11 are VSPA trigger sources via ext_go rather than VSPA interrupt sources, so the most likely issue is trigger routing/enablement ( TMREN , correct TBGEN1/2 ext_go input, and TISTAT verification) rather than a missing VSPA ISR.

Regards