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Writing Data to PSRAM from DSP on RT685

I am using the RT685 platform, connecting a PSRAM through FlexSPI. The PSRAM (ISSI IS66WVR8M8FALL) is connected to PortA2, and there is a QSPI Flash connected to PortA1.

PSRAM was configured to access by AHB, FlexSPI was configured on MCU side after startup, then after a few minutes, wrote data from DSP side. When writing data from DSP side, there were some 0x00 data in the PSRAM, and the data looks regular. To debug this issue, I wrote 192 bytes 0x32 at once and then 0x33 ...

There is no problem of writing and reading data from MCU side. This issue only occurred when writing data from DSP side.

The configuration of FlexSPI,

const flexspi_config_t FLEXSPI_config = {
  .rxSampleClock = kFLEXSPI_ReadSampleClkLoopbackInternally,
  .enableSckFreeRunning = false,
  .enableDoze = true,
  .enableHalfSpeedAccess = false,
  .enableSckBDiffOpt = false,
  .enableSameConfigForAll = false,
  .seqTimeoutCycle = 65535,
  .ipGrantTimeoutCycle = 255,
  .txWatermark = 8U,
  .rxWatermark = 8U,
  .ahbConfig = {
    .ahbGrantTimeoutCycle = 255,
    .ahbBusTimeoutCycle = 65535,
    .resumeWaitCycle = 32,
    .buffer = { 
      { .priority = 0, .masterIndex = 0U, .bufferSize = 256U, .enablePrefetch = true },
      { .priority = 1, .masterIndex = 0U, .bufferSize = 256U, .enablePrefetch = true },
      { .priority = 2, .masterIndex = 0U, .bufferSize = 256U, .enablePrefetch = true },
      { .priority = 3, .masterIndex = 0U, .bufferSize = 256U, .enablePrefetch = true },
      { .priority = 4, .masterIndex = 0U, .bufferSize = 256U, .enablePrefetch = true },
      { .priority = 5, .masterIndex = 0U, .bufferSize = 256U, .enablePrefetch = true },
      { .priority = 6, .masterIndex = 0U, .bufferSize = 256U, .enablePrefetch = true },
      { .priority = 7, .masterIndex = 0U, .bufferSize = 256U, .enablePrefetch = true }
    },
    .enableClearAHBBufferOpt = true,
    .enableReadAddressOpt = false,
    .enableAHBPrefetch = false,
    .enableAHBBufferable = true,
    .enableAHBCachable = false
  }
};

Configuration of PSRAM,

flexspi_device_config_t FLEXSPI_config_Device_SPIRAM = {
   .flexspiRootClk       = SPIRAM_ROOT_CLOCK_HZ,
   .isSck2Enabled        = false,
   .flashSize            = SPIRAM_SIZE_KBYTES,
   .CSIntervalUnit       = kFLEXSPI_CsIntervalUnit1SckCycle,
   .CSInterval           = 2,
   .CSHoldTime           = 3,
   .CSSetupTime          = 3,
   .dataValidTime        = 0,
   .columnspace          = 0U,
   .enableWordAddress    = false,
   .AWRSeqIndex          = SPIRAM_LUT_SEQ_IDX_WRITE,
   .AWRSeqNumber         = 1U,
   .ARDSeqIndex          = SPIRAM_LUT_SEQ_IDX_READ,
   .ARDSeqNumber         = 1U,
   .AHBWriteWaitUnit     = kFLEXSPI_AhbWriteWaitUnit2AhbCycle,
   .AHBWriteWaitInterval = 1,
   .enableWriteMask      = false,
};

Does anyone have idea about this problem?

i.MXRT 600

Re: Writing Data to PSRAM from DSP on RT685

Hi @VincentW

I think the issue is most likely caused by incorrect FlexSPI AHB configuration for multi-master access.

Currently, all AHB buffers are assigned to master 0.

 .buffer = { 
      { .priority = 0, .masterIndex = 0U, .bufferSize = 256U, .enablePrefetch = true },
      { .priority = 1, .masterIndex = 0U, .bufferSize = 256U, .enablePrefetch = true },
      { .priority = 2, .masterIndex = 0U, .bufferSize = 256U, .enablePrefetch = true },
      { .priority = 3, .masterIndex = 0U, .bufferSize = 256U, .enablePrefetch = true },
      { .priority = 4, .masterIndex = 0U, .bufferSize = 256U, .enablePrefetch = true },
      { .priority = 5, .masterIndex = 0U, .bufferSize = 256U, .enablePrefetch = true },
      { .priority = 6, .masterIndex = 0U, .bufferSize = 256U, .enablePrefetch = true },
      { .priority = 7, .masterIndex = 0U, .bufferSize = 256U, .enablePrefetch = true }
    },

You can try to assign one buffer to the dsp.

Enabling AHB write buffering (enableAHBBufferable = true) may delay or merge writes, which is not suitable for PSRAM and can lead to missing data.

You can try to

enableAHBBufferable = false;

BR

Harry

Re: Writing Data to PSRAM from DSP on RT685

Thanks Harry.
Is there any meaning of .mastIndex ? or is there any range of it?
I just want to know how to choose the Master ID.

Re: Writing Data to PSRAM from DSP on RT685

Hi Harry,

I tried to disable the buffer of AHB TX, it didn't help to solve this issue.

enableAHBBufferable = false;

Do you know if there is anything about the cache, which may cause this?

Thanks a lot in advance.

Re: Writing Data to PSRAM from DSP on RT685

Hi @VincentW

Based on the relevant documents of RT600/RT685,. buffer [] corresponds to AHB RX Buffer, which is the read path buffer,
The range of. priority is from 0 to 7, with 7 being the highest and 0 being the lowest;
. mastIndex is the AHB Master ID used to allocate a certain AHB RX buffer to a master for read access. The documentation states that FlexSPI will select RX buffer based on master ID; A master does not support allocating multiple RX buffers.
The unit of. bufferSize in the SDK structure is bytes, but the unit of the underlying register BUFSZ is 64 bits

You can refer to the RT600 user manual for details.

BR

Harry

Re: Writing Data to PSRAM from DSP on RT685

Hi @VincentW

I will discuss with our internal team and get back to you as soon as possible.

BR

Harry

Re: Writing Data to PSRAM from DSP on RT685

Hi @VincentW

Yes, you are right.

 xthal_set_region_attribute((void *)0x08000000,0x800000,XCHAL_CA_BYPASS,0);

BR

Harry

Re: Writing Data to PSRAM from DSP on RT685

Hi @VincentW

After we tested.

If the read and write operations of FlexSPI PSRAM are handled by different masters, namely CM33 and DSP, there are two points that need attention:

1. For DSP, the access to FlexSPI bypasses Cache64, whereas for CM33, Cache64 on the access path to FlexSPI. See the first diagram for details.

So I suggest to disable cache64 when CM33 read - DSP write and CM33 write - DSP read.

2. For HiFi4 dsp, there are instruction cache and data cache in it. And for the PSRAM access, the access is cacheable.

So if DSP write the PSRAM, then the CM33 reading may be inconsistent.

So I suggest to set non-cache access for FlexSPI PSRAM when CM33 read - DSP write and CM33 write - DSP read.

The data we tested is consistent.

BR

Harry

Re: Writing Data to PSRAM from DSP on RT685

Thanks Harry.

Actually, I included 2 issues related the accessing of SPI RAM.

Both were using the SPI RAM (8MB) connected to FlexSPI port A2, there is another SPI Flash (8MB) connected to port A1. SPI RAM address was mapped to 0x08800000.

# 1 Data written to SPI RAM from DSP core.

// copy data into SPI RAM from DSP core
uint8_t * dst = (uint8_t *)0x08800000;
uint8_t src[192] = { 0x30 };
memcpy(dst, src, sizeof(src));

# 2 Data written from SPI RAM into SD card on MCU core

We were using this file system, https://doc.segger.com/UM02001_emFile.html#FS_Write

https://doc.segger.com/UM02001_emFile.html#FS_FOpen

uint8_t * src=(uint8_t*)0x08800000;

FS_FILE * pFile = FS_FOpen("\test.dat", "wb+");
if (pFile)
{
    FS_Write(pFile, src, 0x8000);
    FS_FClose(pFile);
}

in the low level code of emFile, it will use the src point for the ADMA, similar to

USDHC_SetADMA1Descriptor(, , (const uint32_t *)0x08800000, 0x8000, );

I suppose you could test on EVK with ,

f_write()

Re: Writing Data to PSRAM from DSP on RT685

Hi @VincentW

Can you share your code?

I want to reproduce this issue on my end.

BR

Harry

Re: Writing Data to PSRAM from DSP on RT685

Hi @VincentW

"I am afraid I could not share the code due to some commercial code included, sorry about that."

We need to write code to reproduce the issue you mentioned earlier.

"From my understanding of the UM11147, the mapped address of SPI RAM could not be accessed by the ADMA of uSDHC, am I right?"

Yes you are right.

BR

Harry

Re: Writing Data to PSRAM from DSP on RT685

Thanks Harry.

I am curious about how to configure that `.buffer`, e.g.,

what's the range of `.priority`?

how to configure the `.masterIndex`?

what size should the `.bufferSize` be? as my understand, total bufferSize should be 2048.

I didn't find any material indicating how to configure, if there is a document or some comment in `fsl_flexspi.h`, I suppose that will be very helpful.

In my case, I plan to let DSP writing data into PSRAM, then let MCU reading out. As my understand, that `.buffer` is for AHB RX, so in my case, should I assign any buffer for DSP?

Re: Writing Data to PSRAM from DSP on RT685

Thanks Harry. I have another question, could I use the PSRAM mapped address for the uSDHS's ADMA in MCU core? E.g., if I mapped the PSRAM address to 0x08800000, could I use the pointer

uint8_t * dataAddr = (uint8_t*)0x08800000;

for the ADMA?

Re: Writing Data to PSRAM from DSP on RT685

Thanks Harry, that's really helpful.

Could I disable the cache in DSP core like this?

int main(void)
{
    void *spiRamStart;
    *(uint32_t *)(&spiRamStart) = 0x08800000;
    xthal_set_region_attribute(spiRamStart, 0x00800000, XCHAL_CA_BYPASS, 0);

    // ...
}