I am working with the i.MX8QXP processor, which supports sideband ECC. I am considering using five 8‑bit DDR3L DRAM chips and combining them via bit‑splicing (concatenation) to form a 40‑bit total memory width.
My question is:
Will the sideband ECC function work correctly with this 40‑bit configuration (5× 8‑bit chips), or are there any limitations regarding the data width, chip count, or sideband ECC implementation on this SoC?
Any advice or reference to relevant documentation would be greatly appreciated.
Thank you.
My proposed implementation is to use five 8‑bit DDR3L chips (not two 16-bit + an 8-bit) and combine them via bit‑splicing to form a 40‑bit bus (four chips for 32‑bit data, one chip for 8‑bit ECC).
My questions is this 5‑chip × 8‑bit configuration supported by the i.MX8QXP DDR controller when Sideband ECC is enabled?
I have already looked at the attached document, but it does not clearly address these hardware implementation details.
Hi @yuyang12
The Sideband ECC is only supported on a 40-bit (32 +
When the Sideband ECC is enabled, an additional data bus is used for the ECC. The actual DRAM data width is greater than the
current "DRAM_DATA_WIDTH". When enabled, it widens the DDR PHY Interface (DFI) data width to accommodate the extra ECC
bytes. 1 ECC byte is added per 1 ECC lane.
About more information, you can refer attachment file.
B.R
Hi @yuyang12
we do not support 5‑chip × 8‑bit configuration supported by the i.MX8QXP DDR controller when Sideband ECC is enabled.
B.R