In our custom board based on LX2160, there are no SPDT switches available to control the power rails through software.
However, our objective is to reduce the power consumption contributed by the USB, WiFi, BT, PoE, and Cellular modules.
Current observations and approach followed from our side:
1. WiFi, BT, and Cellular modules are connected through PCIe.
We observed that these can be disabled through SerDes configuration.
By configuring SerDes protocol with S2 = 9, all corresponding lanes are configured as SGMII instead of PCIe, thereby effectively disabling the PCIe-connected modules.
2. USB modules do not appear to have similar SerDes-based disable options.
For USB, we are currently trying GPIO-based disable using:
USB1_MUX_EN
USB2_MUX_EN
RCW configuration has already been verified, and the corresponding pins are confirmed to be configured as GPIO.
However, even after driving these GPIOs for disable operation, the expected power reduction is not observed.
3.PoE module (AQR113c is used for ethernet)
Please provide your comments/suggestions on any additional files or configurations that may need to be modified for complete disablement and power reduction.
Is it possible to power down the USB, WiFi, BT, PoE, and Cellular modules when idle? Or this is some different configuration of the product where these interfaces will not be used at all?
Please note even when an interface is unused, power still needs to be applied to its power rail. LX2160A does not support removing power from its rails.
If power is removed from interfacing devices, it needs to be ensured that leakage will not happen to LX2160A I/O's
So what you can do:
1) Maximun power is consumed by the cores. SDK supports taking the CPU to a lower frequency when not used to save on power consumption.
Refer Power management - [Layerscape Software Development Kit User Guide | NXP Semiconductors|https://docs.nxp.com/bundle/GUID-487B2E69-BB19-42CB-AC38-7EF18C0FE3AE/page/GUID-2E8E375E-7DCD-4671-B...]
2) Unused IP's can be clock gated through DEVDISR. However once disabled they cannot be enabled.
3) If SerDes lanes are unused, they can be powered down. Refer section 26.10.2 Unused Lanes in LX2160A Reference manual
4) When a SerDes protocol is chosen through RCW setting, it also configures registers relevant to that protocol as per protocol requirement. So reconfiguring lanes is not the correct way.
5) From the schematic snippet, you have configured SerDes#2 for SRDS_PRTCL_S2 =3 but only a single lane is used. You can use SRDS_PRTCL_S2=11 and power down unused lanes as per (4). Similar mechanism could be applied to other SerDes.
6) If Gen3 is unused for PCIe, then PLLF can be powered down. Similarly unused PLL can be powered down
Thanks
How are you measuring power consumption?
Please note that for SerDes lanes, you will need to check on the 0.9V and 1.8V power lanes that supply SerDes I/O's
For DFS, check the power consumption of VDD (0.8V) supply.
Since this is your custom board, do you have power measurment circuitry for power rails?
If you are emasuring at the input of your custom board, I am not sure how much difference you would see. It will also depend on the least count of your measurment.
To check, you may operate the core/platform at a lower configuration. Check the Design checklist and it has graphs for VDD rail power consumption.
Hi,
Thanks for your timely response. I have attached my observations and test results for the points you shared regarding the power optimization suggestions. Please review them and let us know if any additional checks or configurations are recommended.
| Keypoints | Observations |
| CPU hotplug / frequency scaling observation | We tested CPU hotplug, CPU frequency scaling, and different CPU modes using: lscpu | grep line Observations: On-line CPU(s): 9 Off-line CPU(s): 0-8,10-15 However, no measurable power reduction was observed in any of these cases. |
| Unused IP clock gating through DEVDISR | We understand that unused IPs can be clock gated through DEVDISR.However, since disabling these blocks is not reversible without reset, we consider this approach high risk and therefore not recommended for our current testing. |
| Unused SerDes lane power-down | Register writes are successful. However, no noticeable power consumption reduction has been observed so far. |
| SerDes protocol configuration optimization PLL power-down for unused Gen3 PCIe | Applied configuration: |
Hi,
We are measuring consumption with these current sensors connected to BMC, where VCC_12V is sensing the input of custom board and VCC_0V8 is sensing the input of NXP(LX2160A) chipset
Also when flashing(these are measured in VCC_12V i.e, total power consumption)
- using CodeWarrior (could see a drop around 10W) and
- using ( echo mem > /sys/power/state & echo freeze > /sys/power/state) (could see a drop around 6W)(but under this , as user interaction is not there , it is not recommended for our testing),