2361721_en-US

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

2361721_en-US

2361721_en-US

NAFE 73388 PGA Gain

Hello, I'm having a problem configuring the NAFE73388. The device seems to respond correctly to the configuration and the commands we send it:

We write to the configuration registers, and when we read them back, we get exactly the values we wrote.

The conversion commands (SCSR/SCCR) are accepted, and the ADC performs conversions in the different modes; we’re setting the pointer to 0 (CH_CAL_GAIN_OFFSET) so it uses the Nafe’s default configuration for the mode we’re setting.

The SPI frames we observe on the MISO line correspond to consistent and repeatable data between conversions (we are verifying them directly with the oscilloscope).

If we invert the input polarity, the ADC also returns the corresponding negative value.

The problem we are observing is as follows:

When we configure the channel in single-ended mode with gain = 0.2, the ADC saturates at approximately ±5 V, returning the maximum code (≈ 0x7FFFFF). According to the datasheet, with this configuration we would expect saturation around ±10 V.

That is:

Below ~±5 V, the measurements appear correct.

Above ~±5 V, the ADC begins to saturate.

We would like to confirm whether there might be any additional configuration aspects that are limiting the effective input range (for example, a system register, input mode, or a specific condition of the HV path or ADC PGA), or if there are any specific considerations we should take into account to achieve the full expected range with gain = 0.2.


Re: NAFE 73388 PGA Gain

Hello AlexCp


I am starting to work on your case, I will contact you soon.

Re: NAFE 73388 PGA Gain

Yes you are right at gain=0.2 the part supports +/-10V in single ended mode as defined in the input range table of EC. Our EVB support all these input range conversions. What hardware are you using?

RafaR_0-1781118223159.png

the below registers parameter (highlighted yellow) value as 000 & 0000 (written below):

RafaR_1-1781118280150.png

Can you please clarify what you means by “the ADC performs conversions in the different modes”


The factory Gain & offset coefficients for each gain are saved in specific pointers as mentioned in table 12. The pointer location in Ch_Config1is selected in accordance to Table12 to use correct factory coefficient for particular gain setting/input range. So if you are using gain=0.2x(VIN_SE=10V) in CH_CNFIG0, then the factory cal pointer 0 should be used CH_CONFIG1-> CH_CAL_GAIN_OFFSET[3:0]=0000 as per table 12. Similarly, for gain=0.8x (VIN_SE=+/-2.5V), set CH_CONFIG0->GAIN[2:0]=010 and CH_CONFIG1-> CH_CAL_GAIN_OFFSET[3:0]=0010.

RafaR_2-1781118334981.png

If above pointer is correct, then we need to know the Gain and offset coefficient dialed in the below registers.

RafaR_3-1781118352449.png

If above is all correct, can you readback the Alarm registers right after the saturated conversion code are captured.

RafaR_4-1781118381802.png

Please also share the information on input setup – source of input, any circuitry at the input channel, are they measuring the voltage at the input pins of the channel they are converting? Is this issue happening in all conversion modes – SCSR, SCCR, MCSR, MCMR?

I hope this information has helped you, please let me know if you need help with anything else.
Have a great day and best of luck.


Tags (1)
No ratings
Version history
Last update:
‎06-11-2026 02:40 AM
Updated by: