2360719_en-US

[#1]

i.MX95 RMII (ETH1_RMII_REF50_CLK)

Hi All,

Trying to connect an RGMII PHY and an RMII only PHY to the imx95.

Based on the follwing statement from the reference manual we have tried to connect the ETH1_RMII_REF50_CLK to ENET2_TD2:

p206 i.MX 95 Applications Processor Reference Manual, Rev. 5, 2026-03-30
"ENET_REF_CLK_ROOT must be configured with CLOCK_ROOT61_CONTROL to 250 MHz for RMII and RGMII modes. For RMII mode, ENET_REF_CLK_ROOT is internally divided by 5 to generate the RMII_REF50_CLK"

But we're only seeing 250mhz on that pin.

Using:

/* ---------- NETC fabric: port 1 RGMII → RMII -------------------------  */

&netc_prb_ierb {
	netc-interfaces = ;	/* port 1: LAN8720AI        */
	netc-rmii-clk-dir = ;	/* port 1: MAC drives 50MHz */
	assigned-clock-rates = <666666666>, <250000000>;
	/* ENETREF = 250 MHz for RGMII; RMII gets 50 MHz via TD2 hw /5 divider */
};

/* ---------- Pinctrl: ENET2 pads → RMII functions ----------------------  */

&pinctrl_enetc1 {
	fsl,pins = <
		/* Reset GPIO — drives LAN8720AI nRST (active-low)         */
		IMX95_PAD_ENET2_MDC__GPIO4_IO_BIT14			0x3fe
		/* RMII TX */
		IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RMII_TXD0	0x57e
		IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RMII_TXD1	0x57e
		IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RMII_TX_EN	0x57e
		/* RMII RX */
		IMX95_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RMII_RXD0	0x57e
		IMX95_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RMII_RXD1	0x57e
		IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RMII_CRS_DV	0x57e
		/* RMII 50 MHz ref clock: hw /5 divider outputs on TD2 to PHY CLKIN */
		IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RMII_REF50_CLK	0x4000057e
		/* RMII RX error */
		IMX95_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RMII_RX_ER	0x57e
	>;
};

/* ---------- MDIO bus: disable broadcast on SoM PHY, add LAN8720 ------  */

&ethphy0 {
	realtek,broadcast-disable;
};

&netc_emdio {
	ethphy_lan: ethernet-phy@0 {
		compatible = "ethernet-phy-id0007.c0f0";
		reg = <0>;
		max-speed = <100>;
		reset-gpios = <&gpio3 14 GPIO_ACTIVE_LOW>;
		reset-assert-us = <10000>;
		reset-deassert-us = <80000>;
		smsc,disable-energy-detect;
	};
};

/* ---------- ENETC port 1: RMII + LAN8720 via MDIO --------------------  */

&enetc_port1 {
	phy-mode = "rmii";
	phy-handle = <&ethphy_lan>;
};

Re: i.MX95 RMII (ETH1_RMII_REF50_CLK)

Hi @ArcherLang 

You can refer the below dts file at the link below:

https://github.com/nxp-imx/linux-imx/blob/lf-6.18.y/scripts/dtc/include-prefixes/arm64/freescale/imx...

I have tested the CLK of my IMX95 EVK board, the clk is 50Mhz.

B.R

Re: i.MX95 RMII (ETH1_RMII_REF50_CLK)Also, we can get RMII working by setting the assigned clockrate to 50,000 - but that breaks rgmii on the other phy.Re: i.MX95 RMII (ETH1_RMII_REF50_CLK)

Thanks @pengyong_zhang !

Didn't find the dts on that branch, but I did track it down here:
https://github.com/nxp-imx/linux-imx/blob/lf-6.12.y/arch/arm64/boot/dts/freescale/imx95-19x19-evk-tj...

Looks like we were working with an old kernel (6.6.xx) that doesn't have NETC_BLK_CTL. 

Will update to 6.12xx and test.

Re: i.MX95 RMII (ETH1_RMII_REF50_CLK)

Hi we've compiled the new bsp and kernel to test the patch, still getting the same result.

See decompiled dtb attached.

dtb is applied as we ARE seeing a clock on TD2, it's just the wrong frequency as tested with oscilliscope.

Does IMX95 support 1xRGMII + 1x RMII?