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2358152_ja-JP

2358152_ja-JP

eno0を設定できないのはなぜですか？また、MDIO信号ピンの信号レベルが変化しないのはなぜですか？

こんにちは、

私はLS1028A評価ボードを使用しています。私はドキュメントに従って、bld -m ls1028ardb コマンドを使用して LS1028A のブートイメージを作成しました。SDカードにイメージを書き込んでシステムを起動した後、システム内でeno0を設定することができません。エラー内容は以下のとおりです。

root@ls1028ardb:~# ifconfig eno0 192.168.0.110
[  312.156125] net eno0: could not attach to PHY
SIOCSIFFLAGS: No such device

ログを確認したところ、以下のエラーが見つかりました。

fsl_enetc_mdio 0000:00:00.3: probe with driver fsl_enetc_mdio failed with error -5

ログによると、MDIOドライバがプローブに失敗し、PHYの接続が妨げられたことが示されています。さらに、ログにはenethだけでなく、4つのスイッチポートすべてにおいてPHY接続タイムアウトが発生していることが示されています。

私はオシロスコープを使用して、EMI1_MDIOピンとEMI1_MDCピンの信号レベルを測定しました。EMI1_MDCは670kHzの矩形波を連続的に出力しますが、これは正常な動作のようです。しかし、U-Bootでmdioコマンドを使用してPHY IDを照会する場合、EMI1_MDIOピンは常にハイレベルのままになります。U-Bootコマンドとその出力結果を以下に示します。

=> mdio list
enetc-0: emdio-3:
2 - AR8031/AR8033 <--> enetc-0
10 - Generic PHY <--> swp0
11 - Generic PHY <--> swp1
12 - Generic PHY <--> swp2
13 - Generic PHY <--> swp3
enetc-2: felix-switch:
=>
=> mdio read enetc-2 2 0x02
Reading from bus enetc-2 PHY at address 2:
2 - 0x83
=> mdio read enetc-2 2 0x03
Reading from bus enetc-2 PHY at address 2:
3 - 0xe400

=> mdio read enetc-0 2 0x02
Reading from bus enetc-0
PHY at address 2:
2 - 0x0
=> mdio read enetc-0 2 0x03
Reading from bus enetc-0
PHY at address 2:
3 - 0x0
=> mdio read emdio-3 2 0x00
Reading from bus emdio-3
PHY at address 2:
TT0 - 0x9200
=> mdio read emdio-3 2 0x02
Reading from bus emdio-3
PHY at address 2:
TT2 - 0x9200
=> mdio read emdio-3 2 0x03
Reading from bus emdio-3
PHY at address 2:
TT3 - 0x9200
=>

問題はこの部分にあるのではないかと疑っています。しかし、RCW、デバイスツリー、ハードウェアを徹底的に確認しましたが、明らかなエラーは見つかりませんでした。以下は、起動プロセスにおけるタイムアウトログです。

NOTICE:  Fixed DDR on board
NOTICE:  4 GB DDR4, 32-bit, CL=11, ECC on
NOTICE:  BL2: v2.12.0(release):lf-6.12.20-2.0.0
NOTICE:  BL2: Built : 14:45:11, Dec  4 2025
NOTICE:  BL2: Booting BL31
NOTICE:  BL31: v2.12.0(release):lf-6.12.20-2.0.0
NOTICE:  BL31: Built : 14:45:14, Dec  4 2025
NOTICE:  Welcome to ls1028ardb BL31 Phase

U-Boot 2025.04 (Dec 04 2025 - 14:45:02 +0800)

SoC:  LS1028A Rev1.0 (0x870b0110)
Clock Configuration:
       CPU0(A72):1500 MHz  CPU1(A72):1500 MHz
         Bus:      400  MHz  DDR:      1600 MT/s
Reset Configuration Word (RCW):
       00000000: 3c004010 00000030 00000000 00000000
       00000010: 00000000 018f0000 0030c000 00000000
       00000020: 020031a0 00002580 00000000 00003296
       00000030: 00000000 00000010 00000000 00000000
       00000040: 00000000 00000000 00000000 00000000
       00000050: 00000000 00000000 00000000 00000000
       00000060: 00000000 00000000 200e705a 00000000
       00000070: bb580000 00000000
Model: LS1028A RDB Board
Board: LS1028A Rev1.0-RDB, Version: C, boot from SD
FPGA: v8 (RDB)
SERDES1 Reference : Clock1 = 100.00MHz Clock2 = 100.00MHz
DRAM:  3.9 GiB
DDR    3.9 GiB (DDR4, 32-bit, CL=11, ECC on)
Using SERDES1 Protocol: 47960 (0xbb58)
PCIe1: pcie@3400000 Root Complex: no link
PCIe2: pcie@3500000 Root Complex: no link
Core:  58 devices, 26 uclasses, devicetree: separate
WDT:   Started watchdog@c000000 with servicing every 1000ms (60s timeout)
WDT:   Started watchdog@c010000 with servicing every 1000ms (60s timeout)
MMC:   FSL_SDHC: 0, FSL_SDHC: 1
Loading Environment from MMC... Reading from MMC(0)... *** Warning - bad CRC, using default environment
EEPROM: Invalid ID (ff ff ff ff)
In:    serial
Out:   serial
Err:   serial
SEC0:  RNG instantiated
Net:   TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT
Warning: enetc-0 (eth0) using random MAC address - 3a:b9:c4:9e:93:20
eth0: enetc-0
Warning: enetc-2 (eth1) using random MAC address - 62:d9:2b:9d:bd:a5 , eth1: enetc-2TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTPHY reset timed out TTTTTTTTTTTTT, eth2: swp0TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTPHY reset timed out TTTTTTTTTTTTT, eth3: swp1TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTPHY reset timed out TTTTTTTTTTTTT, eth4: swp2TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTPHY reset timed out TTTTTTTTTTTTT, eth5: swp3

これらの問題の原因を特定するのにご協力いただけますでしょうか？

よろしくお願いします。


Re: Why Cannot eno0 Be Configured and Why Is There No Signal Level Change on the MDIO Signal Pin?

dts ファイル arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts では、コメントに従って、以下の修正を行ってください。

&enetc_mdio_pf3 {

sgmii_phy0: イーサネット-phy@2 {

reg = <0x2>;// カスタムボード上の enetc0 の実際の PHY アドレスで PHY アドレスを変更してください。

        };


/* VSC8514 QSGMII クアッド PHY */

qsgmii_phy0: イーサネット-phy@10 {

reg =<0x10> ; // カスタムボード上の実際の PHY アドレス swp0 を使用して PHY アドレスを変更してください。

        };


qsgmii_phy1: ethernet-phy@11 {

reg =<0x11> ;// カスタムボード上のswp1の実際のPHYアドレスでPHYアドレスを変更してください。

        };


qsgmii_phy2: イーサネット-phy@12 {

reg =<0x12> ;// カスタムボード上のswp2の実際のPHYアドレスでPHYアドレスを変更してください。

        };


qsgmii_phy3: イーサネット-phy@13 {

reg =<0x13> ; // カスタムボード上のswp3の実際のPHYアドレスでPHYアドレスを変更してください。

        };

};

Re: Why Cannot eno0 Be Configured and Why Is There No Signal Level Change on the MDIO Signal Pin?

以前は、flex-installerツールをバージョン2108に戻していませんでした。指示通りにUbuntuシステムのフラッシュと起動をすべて完了しました。しかし、eno0ネットワークカードは依然として認識されません。当社のハードウェアは、「spf-39071_a1.pdf」という文書に基づいて作成されたカスタムボードです。eno0ネットワークカードに対応するPHYチップはAR8033からAR8031に変更され、CPLDチップに書き込まれたプログラムはバージョンv8です。

そこで、私は以下の質問をしたいと思います。

  1. AR8033をAR8031に交換した場合、完全な互換性はありますか？また、ソフトウェアの変更は必要ですか？

  2. CPLDチップに書き込まれたプログラムのバージョンは、PHYチップのリセットに影響しますか？

  3. ご提供いただいたプログラムは、この開発ボードに対応し、ネットワークカードを正しく認識できますか？

ログは以下に添付されています。ご返信をお待ちしております。

Re: Why Cannot eno0 Be Configured and Why Is There No Signal Level Change on the MDIO Signal Pin?

上記で提供したログファイルは、あなたが指示した手順に正確に従って設定されています。詳細は下記のスクリーンショットをご覧ください。

Re: Why Cannot eno0 Be Configured and Why Is There No Signal Level Change on the MDIO Signal Pin?

SDカードを展開し、SDカードからUbuntuのルートファイルシステムを起動するには、上記の手順に従ってください。

Ubuntuのrootfsには「ethtool」コマンドがあります。

Re: Why Cannot eno0 Be Configured and Why Is There No Signal Level Change on the MDIO Signal Pin?

eno0の設定がまだできません。EMI1_MDIOピンは常にハイレベルに保持されます。このログファイルから、U-Bootとカーネルの起動プロセスがそれぞれ正常かどうか確認していただけますか？また、提供いただいた3つのファイルは、開発ボード上で正常に起動しますか？正常に起動する場合、私の側のハードウェアに問題がある可能性はありますか？問題が発生した場合、ログから特定できますか？

Re: Why Cannot eno0 Be Configured and Why Is There No Signal Level Change on the MDIO Signal Pin?

以下の手順に従って、LSDK 21.08のプレビルドイメージをダウンロードしてください。

$ wget https://www.nxp.com/lgfiles/sdk/lsdk2108/firmware_ls1028ardb_sdboot.img

$ wget https://www.nxp.com/lgfiles/sdk/lsdk2108/boot_LS_arm64_lts_5.10.tgz
$ wget https://www.nxp.com/lgfiles/sdk/lsdk2108/rootfs_lsdk2108_ubuntu_main_arm64.tgz

次に、それらをSDカードに展開します。

$ wget https://www.nxp.com/lgfiles/sdk/lsdk2108/flex-installer&& chmod +x flex-installer && sudo mv flex-installer /usr/bin

$ flex-installer -i pf -d /dev/sdb

$ flex-installer -f firmware_ls1028ardb_sdboot.img-b boot_LS_arm64_lts_5.10.tgz -r rootfs_lsdk2108_ubuntu_main_arm64.tgz-d /dev/sdb

注：/dev/sdbは、お使いのPC上のSDカードデバイス名です。


次に、SDカードをターゲットボードに挿入し、LS1028ARDBスイッチの設定を以下のように構成して、ターゲットボードがSDカードから起動するように設定します。

ブートソース SW2[1:8] SW3[1:8] SW5[1:8]
SDカード（SDHC1）1000_1000 1111_0000 0011_1001

SDカードからLinuxを起動し、「ethtool」を使用してリンクの状態を確認してください。

Re: Why Cannot eno0 Be Configured and Why Is There No Signal Level Change on the MDIO Signal Pin?U-Boot内からPCにpingすることもできません。また、EMI1_MDCの出力周波数は670kHzでしょうか？弊社のハードウェアエンジニアが、この件について私に確認を求めています。Re: Why Cannot eno0 Be Configured and Why Is There No Signal Level Change on the MDIO Signal Pin?

u-bootからeno0経由で外部にpingできるかどうか確認してください。
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Last update:
‎04-30-2026 02:28 AM
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