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[#1]

Is dynamic SerDes PLL clock diving (10G XFI -> 1G 1000BASE-X) physically supported on LX2160A?

Hey,

I’ve been doing some deep-dive development on the LX2160A (working on a SolidRun board) and I'm running into a brick wall trying to get dynamic SFP hot-swapping to work between 10G and 1G fiber modules. I’m currently on the lsdk-21.08 branch, testing directly with the native runme.sh generated ubuntu-core.img.

My goal is pretty straightforward: I want to boot the SFP cage in 10G (XFI) using the standard RCW, pull the 10G module out, plug in a standard 1G (1000BASE-X) module, and have the link gracefully down-shift without needing a reboot or an RCW reflash.

When I first plugged the 1G module in, phylink threw a -22 (Invalid argument), because the MAC was locked to PHY_INTERFACE_MODE_10GBASER.

To see if I could force the down-shift, I applied the usual community workarounds to drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c file.
I spoofed the phylink capability masks to explicitly allow 1000baseX_Full on a 10G port, and added a bypass to ignore the phy_validate SerDes rejection.

This actually worked perfectly and the -22 error cleared, the ethtool recognized the 1G speeds. But when the kernel reached down to execute the physical change, phy_set_mode_ext() threw a -95 error (operation not supported) straight from the SerDes driver.

I’m hoping someone here can confirm the actual hardware limitations:

1. Is the LX2160A silicon fundamentally incapable of dynamically re-tuning the SerDes PLL clock from 10.3 GHz (10G) down to 1.25 GHz (1G) on the fly?

2. Is the dynamic switching in lsdk-21.08 strictly limited to protocols that already share the same SerDes clock speed (like swapping between 1G SGMII and 1G 1000BASE-X)?

Thanks.

LX2160A 

Re: Is dynamic SerDes PLL clock diving (10G XFI -> 1G 1000BASE-X) physically supported on LX2160A

Hello,

No — you should not expect a lane booted in XFI/10G to hot-swap at runtime to native 1G 1000BASE-X/KX without a SerDes reconfiguration sequence, and that reconfiguration changes the PLL/lane settings that are normally established by the RCW at boot. Your -95 from phy_set_mode_ext() is consistent with the SerDes driver refusing a mode change that requires changing the underlying lane rate/protocol rather than just phylink policy.

For your two specific questions:

1. Can LX2160A dynamically retune a SerDes lane from 10.3125 Gbaud XFI down to 1.25 Gbaud 1G mode “on the fly”?
   Not as a simple live hot-swap transition. The reference manual shows that XFI/SFI uses a different lane rate and PLL setup than 1000Base-KX/SGMII:

   • protocol notation explicitly distinguishes USXGMII/XFI at 10.3125 Gbaud from SGMII at 1.25 Gbaud
   • PLL reference-clock recommendations differ: XFI/SFI uses 156.25 MHz or 161.1328125 MHz, while 1000Base-KX allows 100/125/156.25 MHz 
   • PLL clock-net/VCO recommendations differ: XFI/SFI/10GBase-KR uses 00110b = 10.3125G clock net on 20.625G VCO, while 1000Base-KX uses 00000b or 10000b = 5G clock net 
   • lane divider settings differ: BY_N_RATE_SEL = 000 for XFI/SFI/10GBase-R/10GBase-KR but 010 for 1000Base-KX and 1G SGMII on both TX and RX
   • interface width also differs: XFI/SFI/10GBase-R uses 20-bit, while 1/2.5G SGMII uses 10-bit 

   The manual does define a PLL Reset and Reconfiguration procedure where software can halt the PLL/lanes, change per-PLL settings including VCO frequency and refclk frequency, then restart them. But that is an explicit reconfiguration flow, not an autonomous/live downshift mechanism for an inserted SFP module. It also recommends disabling controllers connected to the lane before doing so. 

2. Is dynamic switching in LSDK 21.08 limited to cases that already share the same SerDes clocking/rate family?
   The LSDK 21.08 guide notes SFP support through phylink in the DPAA2 driver stack, but I did not find documentation claiming native runtime switching between XFI 10G and 1G 1000Base-X/KX on one active lane without SerDes reconfiguration. 
   By contrast, the LX2160A reference manual explicitly provides separate initialization flows for:

   • 1000Base-KX, including enabling the KX AN reference clock, setting PCC8[SGMIIp_KX]=1, and programming SGMII/KX-side registers 
   • XFI/SFI/10GBase-KR/SXGMII, as a different class of protocol with different lane settings [

   That separation strongly indicates runtime changes are only practical when the hardware remains within the same underlying SerDes operating regime, or when a full lane/PLL reconfiguration sequence is performed. 

A few details from the LX2160A docs line up very closely with the behavior you observed:

• The 1000Base-KX sequence explicitly says SGPCS_EN must be set when reconfiguring a port from XFI/SFI/1000Base-KR to SGMII or 1000Base-KX operation. That is a true mode conversion, not just a link-mode advertisement change. 
• PCC8[SGMIIp_KX] must be set before any MDIO initialization of the PCS for 1000Base-KX. 
• The 1000Base-KX path also requires enabling the AN reference clock with PLLnCR1[EX_DLY_SEL]=10, again showing this is a distinct PCS/PLL setup. 

So the key takeaway is: phylink can be made to accept the module logically, but the SerDes still has to support the physical mode transition. On LX2160A, XFI-to-1G is not just an advertisement change; it requires changing lane rate, PLL settings, and PCS mode. [

The available documentation does show that LX2160A has a newer SerDes architecture with software-driven reconfiguration capability, and there is even an application note describing lane reconfiguration between protocol sets on LX2160A. But that note is about a controlled software sequence that changes SerDes protocol assignment and PLL mapping; it is not evidence of seamless SFP hot-swap downshift from XFI to 1G in a running Linux data path. 

So the answer to your practical question on lsdk-21.08 + native LX2160A SFP cage is:

• Boot in XFI, pull 10G optic, insert plain 1G 1000BASE-X module, and expect graceful downshift with no reboot/RCW involvement:  the SerDes programming model argues against it. 
• Switching among protocols that keep the same 10.3125 Gbaud electrical regime is more plausible, because XFI/10GBase-KR/USXGMII@10G share the 10.3125G class in the SerDes documentation.
• Switching between XFI and 1G SGMII/1000Base-KX crosses baud-rate/PLL/PCS boundaries, so it is not a simple hot-plug transition.

On LX2160A, native hot-swapping an SFP lane from 10G XFI to 1G 1000Base-X/KX is not documented as a seamless runtime feature because it requires a real SerDes/PLL/PCS reconfiguration, not just a phylink mode change.

Regards