Hi, NXP experts, I have two S32K3 FXOSC questions to ask:
1. What is the deviation requirement of S32K3 for FXOSC crystal? I can't get this data from the Datasheet.
2. From the Datasheet, I can see that there is no feedback resistor for the FXOSC inside the K3 chip. So I would like to check if there is a 1M feedback resistor inside the K3 chip.
thank you
Thank you for your help.
Regarding the second question, do you normally recommend another feedback resistor outside the FXOSC? I see from "S32K344-WB-DESIGN-FILES" that the FXOSC has a 1MΩ feedback resistor, but not in "S32K3xx - Hardware Design Guidelines -- Rev_D".
I would also like to ask, regarding the PLL loss of lock threshold, what are the units of ±5, ±9, ±17, ±33, and what is the time period impact if quantized in a 1ms task? For S32K312 chip VCO=960M
Hi
A1. I think this depend on customer final application.
If your application for example, requires a high precision clock then you will need a low PPM.
For example, if the customer requires CAN communication. And select AIPS_PLAT_CLK generated by PLL(crystal) as the clock source of CAN.
PLL retains its source clock accuracy, here XTAL clock, so there will be no issue as well using the PLL as CAN protocol clock. An PLL jitter will add some error, but it is x-times smaller comparing XTAL accuracy for typical CAN bit timing.
A2. The S32K3 DataSheet mentions that the FXOSC has an internal feedback resistor, but does not specify its value: To ensure stable oscillations, FXOSC incorporates the feedback resistance internally.
Best Regards,
Robin
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The feedback resistor R168 in the S32K344-WB-DESIGN-FILES is labeled DNP, so it is not actually soldered.
Please wait for me to consult the AE team for details about PLLCAL2[ULKCTL].
Hi Robbin
I'd like to ask, since the K3 crystal oscillator integrates a feedback bias resistor, will there be any impact if a 1M resistor is connected in parallel with the input/output terminals outside the crystal oscillator?
An external 1 MΩ resistor will be connected in parallel with the internal feedback resistor, thus reducing the equivalent feedback resistance.
The feedback resistor Rf affects the amplifier loop gain, and a lower Rf will reduce the loop gain.
This may reduce the oscillation margin, especially under boundary conditions such as low/high temperature, low voltage, large crystal ESR, and load capacitance deviation, it is necessary to verify the startup time, EXTAL/XTAL amplitude, PLL lock, and clock stability.