2352748_en-US

[#1]

RT1052's DCD file SDRAMCR0 and SEMC_DBICR0 registers are configured in contradiction to each other.

Dear NXP.

Hello!

In the RT1052 development board SDK (D:\SDK_2_14_0_MIMXRT1052xxxxB\boards\evkbimxrt1050\lvgl_examples\lvgl_demo_widgets\mdk), in the dcd.c file, there are two registers configured:

①

/* #1.104, command: write_value, address: SEMC_SDRAMCR0, value: 0xF07, size: 4 */
0x40, 0x2F, 0x00, 0x40, 0x00, 0x00, 0x0F, 0x07,

COL:11b - 9 bit
9-8
COL
Column address bit number
00b - 12 bit
01b - 11 bit
10b - 10 bit
11b - 9 bit

This register configures the Column address bit number to 9 bits.

②

/* #1.108, command: write_value, address: SEMC_DBICR0, value: 0x21, size: 4 */

0x40, 0x2f, 0x00, 0x80, 0x00, 0x00, 0x00, 0x21.

COL:0000b - 12 Bits
15-12
COL
Column Address bit width
0000b - 12 Bits
0001b - 11 Bits
0010b - 10 Bits
0011b - 9 Bits
0100b - 8 Bits
0101b - 7 Bits
0110b - 6 Bits
0111b - 5 Bits
1000b - 4 Bits
1001b - 3 Bits
1010b - 2 Bits
1011b - 12 Bits
1100b - 12 Bits
1101b - 12 Bits
1110b - 12 Bits
1111b - 12 Bits

Column Address bit width is set to 12bit.

Are these two register configurations contradictory? Or is there something wrong with my understanding?

(used at the end of a letter introduce a polite salutation)

Salute!

Re: RT1052的DCD文件SDRAMCR0与SEMC_DBICR0两个寄存器配置矛盾

Hi @FromCH0,

Thank you for your interest in the NXP RT product line and we are pleased to be of service to you.

Q: Are these two register configurations contradictory? Or is my understanding wrong?

A: These two settings do not contradict each other.

1: SEMC_SDRAMCR0 is used for SDRAM address multiplexing/mapping, determines the organization of address bits such as Column, Bank, etc., and acts as the Row address setting.

2: SEMC_DBICR0 is the DBI-B control register of SEMC, which belongs to Display Bus Interface control function and does not participate in SDRAM address mapping, so the two registers will not conflict.

I hope the above helps you

Best Regards

May Liu

Re: RT1052的DCD文件SDRAMCR0与SEMC_DBICR0两个寄存器配置矛盾

The reliably identified core purpose of the RT1052's SEMC_DBICR0 is currently to configure the SEMC's DBI-B/8080 display bus bitwidth (for example: 8-bit or 16-bit), which is not involved in SDRAM mapping, and the timing details should be configured primarily in DBICR1.

Re: RT1052的DCD文件SDRAMCR0与SEMC_DBICR0两个寄存器配置矛盾

I probably understand what you mean. However, SEMC_DBICR0 is to configure the Display Bus Interface control function, how to configure this register, there is not much description about this register in the RT1052 reference manual, SEMC_SDRAMCR0 is easy to understand, look up the DATASHEET of the SDRAM, and the corresponding register is The configuration of SEMC_SDRAMCR0 is easy to understand.

Re: RT1052的DCD文件SDRAMCR0与SEMC_DBICR0两个寄存器配置矛盾You are also an employee of NXP. You can't get the details of SEMC_DBICR0 register? Yesterday, I attended one of your meetings, and your technical engineers from NXP's China team would also find it difficult to master the RT series MCUs?