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S32K394 ITCM endurance and boot-time initialization (ECC context)

Hello

With reference to the thread below: Previous ticket with subject: S32K394 FCCU unrecoverable fault NCF_S2 (ECC) - How to identify which memory block triggered it?.

I have a question regarding the ITCM on S32K394.

  1. What is the maximum erase and write endurance (P/E or write cycles) for the ITCM memory?
  2. Is it acceptable to initialize/clear ITCM at boot the same way we typically do for SRAM?
  3. I’m currently assuming ITCM is Flash, but I’m not sure this is correct. Could you please confirm what physical memory type ITCM is on S32K394 (SRAM vs Flash vs something else), and whether repeated initialization impacts endurance?

Any pointers to the relevant reference manual section or datasheet spec would be appreciated.

Thanks in advance.

Fyi, @danielmartynek

Re: S32K394 ITCM endurance and boot-time initialization (ECC context)

Hi @SBalaji,

1.

It is SRAM, so it does not have the limitations as Flash memory.

2.
Yes, it must be initialized before being read, just like any other volatile memory with ECC. 

image.png

3.
It is an SRAM. The key difference is that TCM (Tightly Coupled Memory) is directly connected to the core via a private bus. In contrast, SRAM is accessed through the crossbar switch, which it shares with other system masters.

Refer to Figure 5: Block Diagram in the reference manual.


Regards,

Daniel



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‎04-15-2026 02:54 AM
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