2349052_en-US

[#1]

LX2160A Power Integrity (PI) analysis

Dear Experts

We are currently proceeding with a PCB design using the LX2160A and are planning to perform Power Integrity (PI) analysis.

Could you kindly provide guidance on the following items for setting up appropriate analysis conditions?

1. Recommended target impedance for each power rail
2. Assumed maximum transient current (di/dt) conditions for analysis

Additionally, if there are any recommended PI analysis tools or methodologies, we would appreciate your advice.

Thank you for your support, and we look forward to your response.

Best regards,

Re: LX2160A Power Integrity (PI) analysis

1. Power Rails Overview (LX2160A)

The LX2160A uses multiple independent rails for core logic, SRAM/PLL, SerDes, DDR, and I/O. The exact rail list and nominal voltages are defined in the LX2160A datasheet and reference design and should be treated as authoritative. 

Typical key rails (names vary by schematics):

Rail Function	Typical Nominal Voltage	Notes
Core (VDD)	~0.75–0.85 V	Highest di/dt, most critical for PI
Platform / Cache (VDD_PLAT)	~0.9 V	Large on-die SRAM, sensitive to droop
SerDes Analog	~1.0 V	Noise-sensitive, lower di/dt
SerDes Digital	~0.9 V	Moderate switching activity
DDR VDD	1.2 V	JEDEC-driven, external memory dominates
DDR VPP	2.5 V	Low-current
I/O (VDD_IO)	1.8 V / 3.3 V	Lowest PI criticality

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2. Recommended Target Impedance (Z_TARGET)

Since LX2160A does not publish explicit Z targets, the standard voltage ripple-based method is used:

Ztarget=ΔVallowableΔImaxZ_{target} = \frac{\Delta V_{allowable}}{\Delta I_{max}}Ztarget​=ΔImax​ΔVallowable​​

NXP generally recommends ≤ 3–5% ripple on core-type rails for Layerscape devices (derived from design checklists and reference boards). [static.chipdip.ru], [community.nxp.com]

Practical Target Impedance Values

Rail	Allowable Ripple	Estimated ΔI	Recommended Z_TARGET
Core (VDD)	±3% (≈25 mV)	8–12 A	2–3 mΩ
Platform / SRAM	±3% (≈30 mV)	4–6 A	5–8 mΩ
SerDes Digital	±5%	1–2 A	25–40 mΩ
SerDes Analog	±5%	<1 A	>50 mΩ
DDR VDD	JEDEC	3–5 A	20–30 mΩ
I/O Rails	±5–10%	<2 A	>50 mΩ

Key point:
Only the core and SRAM rails require very aggressive PDN design down into the low milliohm range.

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3. Transient Current / di/dt Assumptions

Core Rail (Critical)

For PI simulation, worst-case transient assumptions are typically:

• ΔI step: 5–8 A
• Edge rate: 1–5 ns
• di/dt: 1–5 A/ns

These represent:

• Simultaneous switching of multiple Cortex-A72 cores
• Cache + datapath accelerator activity (DPAA2, DCE, SEC)

This aligns with how NXP reference boards and design checklists size bulk + high-frequency decoupling. [static.chipdip.ru], [community.nxp.com]

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Other Rails

Rail	ΔI Assumption	di/dt
Platform / SRAM	2–4 A	0.5–1 A/ns
SerDes Digital	0.5–1 A	0.1–0.3 A/ns
DDR VDD	Governed by JEDEC burst	Slower, regulator-dominated
I/O	<0.5 A	Very low

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4. Frequency Range to Analyze

For LX2160A, PI analysis should cover:

• DC → 100 MHz (minimum)
• Up to 300–500 MHz recommended for core rails due to on-die L/C effects

Below ~1 MHz:
Dominated by VRM and bulk capacitors

1–100 MHz:
Board-level MLCCs + planes

100 MHz:
On-package + on-die capacitance (model using package S-parameters if available)

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5. Decoupling Strategy (Reference-Based)

NXP reference designs show a three-tier approach:

1. Bulk
   • 47–330 µF polymer or tantalum per core rail
2. Mid-frequency MLCCs
   • 1–10 µF, X7R, distributed across package perimeter
3. High-frequency MLCCs
   • 0.01–0.1 µF directly under BGA

This approach is consistent with Layerscape RDB layouts. [static.chipdip.ru]

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6. Recommended PI Tools

Widely used tools that work well for LX2160A-class SoCs:

Simulation

• Cadence Sigrity PowerSI
• Ansys SIwave
• Keysight PIPro
• Altium PDN Analyzer (early-stage checks)

Measurement (Post-silicon)

• VNA-based PDN impedance measurement (2-port shunt-through)
• High-bandwidth probing at BGA breakout test points

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7. Methodology Summary (Best Practice)

1. Start with Z_TARGET-based PDN design
2. Build sweep impedance plot (log-log)
3. Eliminate anti-resonance peaks below Z_TARGET
4. Validate with:
   • Worst-case current step
   • Load-transient simulation
5. Correlate against RDB behavior where possible

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8. NXP-Specific Recommendation

NXP explicitly recommends reviewing AN5407 – LX2160A/LX2162A Design Checklist, which includes power use cases and rail current guidance used internally for PDN sizing. [community.nxp.com]

If you have access to NXP Premium Support, you can also request:

• Rail-by-rail worst-case current tables
• Package PDN models (where available)