I am currently evaluating the i.MX95 and have a question regarding the TRDC (TrustZone Resource Domain Controller) configuration.
Is it possible to configure the TRDC to allow two or more cores to access the same hardware resource simultaneously?
Specifically, I would like to know if a single peripheral, such as LPUART1, can be accessed by both the Cortex-M7 and Cortex-M33 cores through TRDC permission settings.
I am fully aware that simultaneous access to a single UART instance by multiple cores can lead to functional conflicts and is generally not recommended for practical operation. However, I am strictly inquiring about whether the TRDC hardware logic supports the assignment of shared access permissions for a single resource across multiple Domain IDs (DIDs).
Could you please confirm if this configuration is supported?
Hi @jsko
From the TRDC's perspective, it is capable of accepting multiple DIDs. However, the TRDC is not responsible for coordinating atomic access to LPUART across multiple domains.
Best Regards,
Zhiming
Could you please confirm if the following scenario is feasible?
The core question is whether one of the two cores can access the LPUART1 while its ownership is assigned to both the CM33 and M7.
5 seconds after boot: LPUART1 ownership is assigned to M7.
10 seconds after boot: LPUART1 ownership is assigned to both M7 and CM33.
15 seconds after boot: M7 uses LPUART1.
20 seconds after boot: CM33 uses LPUART1.
Hi @jsko
I shared flexspi1 between A55 and M7. Due to the M7 image is built in imx-boot container, the M7 will run the flexspi test after power on, then A55 access the flexspi in Uboot.
The core of your question is: who is responsible for coordination? Customers should establish their own coordination mechanism between two cores. They should use the MU to notify each other that the other party is about to use LPUART1, and prevent simultaneous use.
Best Regards,
Zhiming