Hello,
We are using the TJA1101B phy for a few designs. The design uses an external 25 MHz clock source, which is connected to the CLK_IN_OUT (P20) of the phy. In a previous design, XI (P6) and XO (P5) were left floating and the phy worked without any issues, but AN13236 states that, "Pin XI should be connected to ground and pin XO should be left open when using an external clock". The datasheet for the phy makes no mention of this requirement/suggestion.
I have just received a new design which has tied XI to ground, and the phy appears to immediately short and break itself when powering up, with no other changes to its connections. Can someone please confirm that tying XI to ground is safe to do, or is this the cause of the failure? Unfortunately there is very little access to traces on these designs so I cannot remove the ground connection to test.
Thank you for your help,
Adam
Hello @adamrosy ,
Based on the TJA1101 PHY architecture and the recommendations in AN13236, connecting pin XI to GND and leaving XO open is the correct configuration when an external 25 MHz clock is supplied on CLK_IN_OUT.
This connection cannot damage the PHY and is not a root cause for device destruction. The XI pin is electrically inactive when the internal crystal oscillator is disabled and shorting it to ground does not create any harmful current path.
Best regards,
Pavel