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i.MX8QM K4FBE3D4HM-TFCL DDR stresstest faild

Replacing the MT53E768M32D4DT-053AATE with the K4FBE3D4HM-TFCL and ddr stresstest faild.

D320_MB_final_加水印.pdf：schematic diagram.

Log：
*************************************************************************
MX8 DDR Stress Test Version: ER15
Built on Feb 20 2023 15:28:25
*************************************************************************

Waiting for board configuration from PC-end...

--Set up the MMU and enable I and D cache--
- This is the Cortex-A72 core
Adjusting CA72 cache latency
- Check if I cache is enabled
- Enabling I cache since it was disabled
- Push base address of TTB to TTBR0_EL3
- Config TCR_EL3
- Config MAIR_EL3
- Enable MMU
- Data Cache has been enabled
- Check system memory register, only for debug

- VMCR Check:
- ttbr0_el3: 0x13d000
- tcr_el3: 0x2051c
- mair_el3: 0x774400
- sctlr_el3: 0xc01815
- id_aa64mmfr0_el1: 0x1124

- MMU and cache setup complete

*************************************************************************
ARM Clock(CA72): 1596MHz
ARM Clock(CA53): 0MHz
DDR Clock: 1596MHz

============================================
DDR configuration
DDR type is LPDDR4
Data width: 32, bank num: 8
Row size: 16, col size: 10
Two chip selects are used
Number of DDR controllers used on the SoC: 2
Density per chip select: 2048MB
Density per controller is: 4096MB
Total density detected on the board is: 8192MB

Note: As this SoC has more than one DDR Controller, the calculated
density assumes all controllers are being used. Adjust the tested
density per your board configuration if not all controllers are used

********************************************
WARNING! DDR training errors were detected on DDRC 0!
DDR_PHY_PGSR0 = 0x006cc07f
-Write Leveling training error detected
-Read DQS Gate training error detected
-Write DQS2DQ training error detected
-VREF training error detected

Checking byte-level training error status to see which bytes lanes failed above trainings

DDR_PHY_DX0GSR0 = 0x03feffe0
-Write leveling error detected on byte lane 0

DDR_PHY_DX1GSR0 = 0x03feffe0
-Write leveling error detected on byte lane 1

DDR_PHY_DX2GSR0 = 0x03feffe0
-Write leveling error detected on byte lane 2

DDR_PHY_DX3GSR0 = 0x03feffe0
-Write leveling error detected on byte lane 3

DDR_PHY_DX0RSR0 = 0x00000000
DDR_PHY_DX0RSR1 = 0x00000003
-Read DQS Gate Training Error detected on byte lane 0, and rank0 rank1

DDR_PHY_DX1RSR0 = 0x00000000
DDR_PHY_DX1RSR1 = 0x00000003
-Read DQS Gate Training Error detected on byte lane 1, and rank0 rank1

DDR_PHY_DX2RSR0 = 0x00000000
DDR_PHY_DX2RSR1 = 0x00000003
-Read DQS Gate Training Error detected on byte lane 2, and rank0 rank1

DDR_PHY_DX3RSR0 = 0x00000000
DDR_PHY_DX3RSR1 = 0x00000003
-Read DQS Gate Training Error detected on byte lane 3, and rank0 rank1

DDR_PHY_DX0GSR2 = 0xff805000
-Write DQS2DQ training Error detected on byte lane 0
--Oscillator results are all 0s in rank0
--Oscillator results are all 0s in rank1

DDR_PHY_DX1GSR2 = 0xff805000
-Write DQS2DQ training Error detected on byte lane 1
--Oscillator results are all 0s in rank0
--Oscillator results are all 0s in rank1

DDR_PHY_DX2GSR2 = 0xff805000
-Write DQS2DQ training Error detected on byte lane 2
--Oscillator results are all 0s in rank0
--Oscillator results are all 0s in rank1

DDR_PHY_DX3GSR2 = 0xff805000
-Write DQS2DQ training Error detected on byte lane 3
--Oscillator results are all 0s in rank0
--Oscillator results are all 0s in rank1
-Host VREF Training Error detected on byte lane 0, rank0
-Host VREF Training Error detected on byte lane 1, rank0
-Host VREF Training Error detected on byte lane 2, rank0
-Host VREF Training Error detected on byte lane 3, rank0

Recheck DDR initialization and board layout
-Re-check RPA board data bus config worksheet and ensure it is configured correctly
-Make sure to follow NXP's HWDG layout guildelines and default ODT/DSE settings in the RPA
-Check board for manufacturing issues, solder reliablity issues, voltage IR drops
-Perform ABA swap of SoC and/or memory devices to see if issue follows board or chips
********************************************

********************************************
WARNING! DDR training errors were detected on DDRC 1!
DDR_PHY_PGSR0 = 0x006cc07f
-Write Leveling training error detected
-Read DQS Gate training error detected
-Write DQS2DQ training error detected
-VREF training error detected

Checking byte-level training error status to see which bytes lanes failed above trainings

DDR_PHY_DX0GSR0 = 0x03feffe0
-Write leveling error detected on byte lane 0

DDR_PHY_DX1GSR0 = 0x03feffe0
-Write leveling error detected on byte lane 1

DDR_PHY_DX2GSR0 = 0x03feffe0
-Write leveling error detected on byte lane 2

DDR_PHY_DX3GSR0 = 0x03feffe0
-Write leveling error detected on byte lane 3

DDR_PHY_DX2RSR0 = 0x00000000
DDR_PHY_DX2RSR1 = 0x00000003
-Read DQS Gate Training Error detected on byte lane 2, and rank0 rank1

DDR_PHY_DX3RSR0 = 0x00000000
DDR_PHY_DX3RSR1 = 0x00000003
-Read DQS Gate Training Error detected on byte lane 3, and rank0 rank1

DDR_PHY_DX2GSR2 = 0xff80f000
-Write DQS2DQ training Error detected on byte lane 2
--Oscillator results read timeout in rank0
--Oscillator results read timeout in rank1

DDR_PHY_DX3GSR2 = 0xff80f000
-Write DQS2DQ training Error detected on byte lane 3
--Oscillator results read timeout in rank0
--Oscillator results read timeout in rank1
-Host VREF Training Error detected on byte lane 0, rank0
-Host VREF Training Error detected on byte lane 1, rank0
-Host VREF Training Error detected on byte lane 2, rank0
-Host VREF Training Error detected on byte lane 3, rank0

Recheck DDR initialization and board layout
-Re-check RPA board data bus config worksheet and ensure it is configured correctly
-Make sure to follow NXP's HWDG layout guildelines and default ODT/DSE settings in the RPA
-Check board for manufacturing issues, solder reliablity issues, voltage IR drops
-Perform ABA swap of SoC and/or memory devices to see if issue follows board or chips

Re: i.MX8QM K4FBE3D4HM-TFCL DDR stresstest faild

Hi @zhang_rui

your RPA table settings are correct. From your fail log, This seems to be a hardware connection issue. Please double check your HW connection with your HW engineer.

B.R

Re: i.MX8QM K4FBE3D4HM-TFCL DDR stresstest faild

The attachment is DDR datasheet.