2333127_en-US

[#1]

i.MX95: 2ch LVDS output

Hello, 

https://community.nxp.com/t5/i-MX-Processors/iMX95-Two-video-inputs/m-p/2330401#M244435
This is a related question.
We are currently proposing an i.MX95 project to a client, and similar to danielsan-77’s post, it requires two MIPI inputs and two LVDS outputs.
Regarding the MIPI inputs, we believe there will be no issues since we are currently able to handle input from eight cameras using MIPI-CSI2 and MIPI-DSI-CSI2 ports.
My concern is the two-channel LVDS output.
In our case, we will connect the following two independent LCDs via a TI FPDLink3 Serializer:
LVDS1) 800x480@60Hz RGB LCD,
LVDS2) 1280x720@60Hz RGB LCD
Question 1)
The referenced thread mentioned that dual LVDS outputs are possible, and my understanding is that the pixel resolution, size, and pixel clock can be set independently. Is this correct?
Question 2)
I’ve been reviewing the reference manual, but I can't find out. Which registers control the clock, Hsize, Vsize settings for LVDS1 and LVDS2?
Question 3)
I don’t think 2-channel LVDS is implemented in the BSP. Can NXP Engineering Services (Paid service) support this?

Best Regards,

Kanou

Re: i.MX95: 2ch LVDS output

Hi Joanxie, 

Thank you for your prompt response.
You mentioned that it is currently possible to output an independent LVDS signal, but I believe this may actually be difficult.

The reasons are as follows:

The two LVDS displays must be different in resolution and frequency, But I’m guessing that they cannot be independent in any case.

 From the display domain architec
The i.MX95 has one LVDS interface block.
That interface supports:
 - Single-channel LVDS
 - Dual-channel LVDS (odd/even pixel split)

 From the manual

- 165 MHz pixel clock per LVDS channel

- 330 MHz pixel clock in dual-channel mode

A single Display Controller and single LVDS Interface means the two channels share:

- the same pixel clock
- the same timing generator
- the same frame timing (HSYNC/VSYNC)

So both channels are driven by the same display pipeline timing.

Also the single Pixel Interleaver and Pixel Mapper hints that no independent LVDS displays are possible. Split mode and other modes that play with Odd/Even bits should be possible.

Note that the link in Q3 appears to be a tds configuration for splitting a single video into two files (odd and even).

Is this understanding correct?

Best Regards,
kanou

Re: i.MX95: 2ch LVDS output

Question 1)
The referenced thread mentioned that dual LVDS outputs are possible, and my understanding is that the pixel resolution, size, and pixel clock can be set independently. Is this correct?

> this is imx95 lvds performance:165MHz Single 330MHz Dual

Question 2)
I’ve been reviewing the reference manual, but I can't find out. Which registers control the clock, Hsize, Vsize settings for LVDS1 and LVDS2?

>if customer use linux as OS, they don't need change the register to control this, change the ldb clock in the dts

Question 3)
I don’t think 2-channel LVDS is implemented in the BSP. Can NXP Engineering Services (Paid service) support this?

> current bsp has dts file for dual lvds channel support, you can refer to this

https://github.com/nxp-imx/linux-imx/blob/lf-6.12.y/arch/arm64/boot/dts/freescale/imx95-19x19-evk-it...

Re: i.MX95: 2ch LVDS output

Thank you for your response.
In other words, since there is only one PLL, LVDS1 and LVDS2 must share the same clock.
Therefore, I understand that while this would work with the same panel, the following configuration is not feasible:
LVDS1) 800x480@60Hz RGB LCD,
LVDS2) 1280x720@60Hz RGB LCD

BR,

Kanou

Re: i.MX95: 2ch LVDS output

yes correct, The 2 LVDS ports need output same LVDS clock in frequency because only one LDB pll

Re: i.MX95: 2ch LVDS output

yes, The two LVDS ports are same resolution and timing in hardware