2329860_en-US

Yes

enabling mEMAC 3 & 4 in PHYless configuration on ls1046

Good Day!

I've faced some problems enabling mEMAC 3 & 4 in phyless(SOC directly connected to RGMII ports on FPGA) configuration on our ls1046- based custom board.

I'm using 6.18 kernel from NXP QoriQ git, with DPAA SDK drivers. I configured DTS based on LS1046 ARDB DTS, but fixed it to my needs.

My dts section for this configuration(related to dpaa interfaces):

&fman0 {
   ethernet@e4000 { /// 1G fixed RGMII internal connection
      phy-connection-type = "rgmii-id";
      fixed-link = <0 0 1000 0 0>;
   };
   ethernet@e6000 { /// 1G fixed RGMII internal connection
      phy-connection-type = "rgmii-id";
      fixed-link = <0 0 1000 0 0>;
   };
};

During kernel boot I have:

As I result - no interfaces are configured.

So please tell, what can be the problem?

Re: enabling mEMAC 3 & 4 in PHYless configuration on ls1046

1) Fixed to suggested variant - no change.

2) About RCW:

I did all the stuff according to datasheet - EC1 & EC2 should be 0(not 1) to enable RGMII. Is there any error in datasheet? Should I set them to 1 for 100% sure?

3) "Okay" status is surely present in dts.

Re: enabling mEMAC 3 & 4 in PHYless configuration on ls1046

Hello,

The most common reason for mEMAC 3 and 4 failing to initialize on an LS1046A in a phyless/fixed-link configuration is a mismatch in the Device Tree (DTS) syntax or the RCW (Reset Configuration Word) settings.

Here are the most likely causes and fixes for your 6.1 kernel environment:

1. Modern fixed-link Syntax

The <0 0 1000 0 0> syntax is deprecated in newer kernels (5.x/6.x). If the kernel fails to parse the fixed-link, it won't create the interface. Update your DTS to the node-style syntax:

dts

&fman0 {
    ethernet@e4000 { /* mEMAC 3 */
        phy-connection-type = "rgmii-id";
        fixed-link {
            speed = <1000>;
            full-duplex;
            pause;
        };
    };
    ethernet@e6000 { /* mEMAC 4 */
        phy-connection-type = "rgmii-id";
        fixed-link {
            speed = <1000>;
            full-duplex;
            pause;
        };
    };
};

2. RCW Protocol Verification

The LS1046A mEMAC 3 and 4 are mapped to the EC1 and EC2 pins. For these to work as RGMII:

Check your RCW fields: EC1 and EC2 must be set to 0x1 (RGMII).
If your SerDes protocol is set to something that conflicts with these pins, the FMan will fail to initialize the MACs, leading to the "net error" you see.

3. Missing status = "okay"

In the NXP SDK, many mEMAC nodes are disabled by default in the SOC dtsi file. Ensure you explicitly enable them in your board file:

dts

&ethernet@e4000 {
    status = "okay";
};
&ethernet@e6000 {
    status = "okay";
};

4. Clock and Voltage (IOVDD)

Since you are connecting directly to an FPGA:

Ensure the RGMII clocks are being provided. If the FMan doesn't detect a stable clock on the RGMII interface, the driver may time out during initialization.
Verify that the FPGA is providing the 125MHz clock (for 1G) if the LS1046 is not configured to generate it.

If the error in your screenshot mentions "fman_memac_init: could not get PHY", it means the fixed-link wasn't parsed. If it says "fman_memac_init: can't get mac_dev", it is likely a register access/RCW issue.

Regards

Re: enabling mEMAC 3 & 4 in PHYless configuration on ls1046

I've perform all recomendations. Nothing changed.

1) My new dts:

        ethernet@e4000 { /// 1G fixed RGMII internal connection
                status = "okay" 
	        phy-connection-type = "rgmii-id";
		fixed-link {
		        speed = <1000>;
			full-duplex;
			pause;
		};
	};

        /// MAC4
	ethernet@e6000 { /// 1G fixed RGMII internal connection
                status = "okay";
	        phy-connection-type = "rgmii-id";
		fixed-link {
		        speed = <1000>;
			full-duplex;
			pause;
		};
	};

2) RCW:

Despite to the fact that in Reference manual EC1 & EC2 must be set to 0 to enable RGMII 1/2 for MAC 3/4 I've changed to 1. That changed nothing - still MAC3/4 are not up.

My SerDes protocol - 0x2223 - no conflicts as I understand

3) "okay" is present in DTS as I mentioned above

4) About clocking - please clarify this paragraph:

4. Clock and Voltage (IOVDD)
Since you are connecting directly to an FPGA:

    Ensure the RGMII clocks are being provided. If the FMan doesn't detect a stable clock on the RGMII interface, the driver may time out during initialization.
    Verify that the FPGA is providing the 125MHz clock (for 1G) if the LS1046 is not configured to generate it.

 
If the error in your screenshot mentions "fman_memac_init: could not get PHY", it means the fixed-link wasn't parsed. If it says "fman_memac_init: can't get mac_dev", it is likely a register access/RCW issue.

For the time of interface init, FPGA is not working since it's not configured. FPGA configuartion will be performed later. So does it mean,that interface won't be found, as we can see in log:

  2.000819] fsl_dpa soc:fsl,dpaa:ethernet@2: of_find_device_by_node(ethernet@e4000) failed-1
[    2.009272] fsl_dpa soc:fsl,dpaa:ethernet@2: probe with driver fsl_dpa failed with error -22
[    2.017823] fsl_dpa soc:fsl,dpaa:ethernet@3: of_find_device_by_node(ethernet@e6000) failed-1
[    2.026278] fsl_dpa soc:fsl,dpaa:ethernet@3: probe with driver fsl_dpa failed with error -22