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Post Subject: Star analysis/testing of single and dual bit CM4 ECC for TCM

Post Body:

Sent via email by Sean Buller at Star. I have sent him in return Damon/Jia's code and Jia's app note. Kshitij or I will go through these findings and confirm. Nonetheless it was a nice job by the Star engineer.

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I'd like to share some of my finding regarding ECC for CM4 TCM/LMEM enabled through MCM peripheral. My hope is that you can validate and sign-off on these findings if they are consistent with the internal design.

Algorithm Details

- 7-bit Hsiao SECDED (Single Error Correction, Double Error Detection)

H-Matrix (Syndrome column for data bits)

d[00]=0x43 d[08]=0x54 d[16]=0x75 d[24]=0x5D
d[01]=0x45 d[09]=0x58 d[17]=0x76 d[25]=0x5E
d[02]=0x46 d[10]=0x61 d[18]=0x79 d[26]=0x67
d[03]=0x49 d[11]=0x62 d[19]=0x7A d[27]=0x6B
d[04]=0x4A d[12]=0x64 d[20]=0x7C d[28]=0x6D
d[05]=0x4C d[13]=0x68 d[21]=0x4F d[29]=0x6E
d[06]=0x51 d[14]=0x70 d[22]=0x57 d[30]=0x7F
d[07]=0x52 d[15]=0x73 d[23]=0x5B d[31]=0x07

Please validate and confirm H-matrix is correct.

Observation: When write generation is disabled, the hardware writes a fixed ECC value of 0x38 regardless of the data value.
NOTE: This is inconsistent with prior understanding that the ECC value gets set to 0 when write generation is disabled.

Observation: MCM[LMFATR] bits 23-16 is marked RESERVED, read-only, and always has the value 0. However, I observed that these bits contain the syndrome. Can you confirm?

Observation: ITCM and DTCM are both 32-bit and have a 7-bit ECC per 32-bit payload. Can you confirm that neither ITCM or DTCM require 64-bit access to prime ECC?

Observation: Injecting a double-bit error with MCM[LMDRn].CF0[3] PFE - Parity Fault Enable set to 1 (enabled) results in a BUS error at the address where the double-bit error was detected?

Self-test procedure

Important Note: The reason these tests work is because the ECC bits of 0xAAAAAAA1 is exactly 0x38, which is the value the ECC bits are observed to get reset to after write generation is disabled.
Any value I write at step 8 that has ECC bits of 0x38 and write a value at step 10 with 1-bit flipped, will properly yield single-bit error and be corrected.

Examples of single-bit errors where ECC bits of values in step 8 yield 0x38.
Step 8: 0x800005FC Step 10: 0x800005FD
Step 8: 0x8585856F Step 10: 0x8585856B
Step 8: 0x9B9B9B4D Step 10: 0x9B9B8B4D

Can you confirm that the ECC bits get reset to 0x38 when write generation is disabled?

The following tests would be executed both on an address in ITCM and an address in DTCM.

Single-bit error test

1. Disable non-correctable ECC interrupt MCM[LMPECR].ERNCI
2. Enable non-correctable ECC reporting MCM[LMPECR].ERNCR
3. Disable 1-bit ECC interrupt MCM[LMPECR].ER1BI
4. Enable 1-bit ECC reporting MCM[LMPECR].ER1BR
5. Enable write generation
6. Enable read verification
7. Disable parity fault enable
8. Write 0xAAAAAAA1
o This yields ECC bits of 0x38 -- this is very important, because ECC bits get RESET to 0x38 when write generation is disabled
9. Disable write generation
10. Write 0xAAAAAAA0
o This is a single-bit error
11. Enable write generation
12. Read back address
o Observe value at address was CORRECTED to 0xAAAAAAA1
o Observe MCM[LMPEIR].EIB[8] or MCM[LMPEIR].EIB[9] are set (depending on if address was ITCM or DTCM)
13. Clear errors MCM[LMPEIR].E1B and MCM[LMPEIR].ENC

Double-bit error test

1. Disable non-correctable ECC interrupt MCM[LMPECR].ERNCI
2. Enable non-correctable ECC reporting MCM[LMPECR].ERNCR
3. Disable 1-bit ECC interrupt MCM[LMPECR].ER1BI
4. Enable 1-bit ECC reporting MCM[LMPECR].ER1BR
5. Enable write generation
6. Enable read verification
7. Disable parity fault enable
8. Write 0xAAAAAAA1
o This yields ECC bits of 0x38 -- this is very important, because ECC bits get RESET to 0x38 when write generation is disabled
9. Disable write generation
10. Write 0xAAAAAAA2
o This is a double-bit error
11. Enable write generation
12. Read back address
o Observe MCM[LMPEIR].ENC[0] or MCM[LMPEIR].ENC[1] are set (depending on if address was ITCM or DTCM)
13. Clear errors MCM[LMPEIR].E1B and MCM[LMPEIR].ENC

Please confirm that running this test procedure:
1. Correctly tests single-bit error
2. Correctly tests double-bit error
3. Is recoverable and does not have any unintended side-effects
o I have validated that after re-enabling interrupts after the test, I can get the appropriate interrupts on subsequent errors.

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Link to post: Star analysis/testing of single and dual bit CM4 ECC for TCM