2315088_en-US

For S32G274A multi-core scenario, can the first 0x9100 bytes of fip.bin be neglected?

When making ATF image for BSP42, we get information like this:

Boot Core: A53_0

IVT Location: QSPI

Load address: 0x342f8f00

Entry point: 0x34302000

Entry point - Load address = 0x9100

it's BL2 that sits at offset 0x9100 of fip.bin. So is "Entry point" refering to BL2?

For multi-core scenario, MCU runs bootloader to load BL2 for A53.

If BL2 is the entry point, should bootloader just copy from offset 0x9100 of fip.bin(BL2) to 0x34302000 of RAM space(neglect the first 0x9100 bytes)？

GoldVIP

Re: For S32G274A multi-core scenario, can the first 0x9100 bytes of fip.bin be neglected?

Hello, @wansp

Thanks for your post

The bootloader will move the data from QSPI to the Load address(SRAM), they would not be neglected.

Chenyin