2314200_en-US

はい

IMX8MP Board PCIe Phy link never came up

Hi NXP Team,

I am working on a custom board based on i.MX8M Plus, where the PCIe Root Complex (RC) is the i.MX8MP and the PCIe End Point (EP) is an FPGA.

Currently, PCIe initialization starts, but the PCIe PHY link never comes up, and the endpoint is not detected. Below is the relevant log output:

sh-5.2# dmesg | grep pci
[ 3.115342] imx6q-pcie 33800000.pcie: host bridge /soc@0/pcie@33800000 ranges:
[ 3.122709] imx6q-pcie 33800000.pcie: IO 0x001ff80000..0x001ff8ffff -> 0x0000000000
[ 3.130996] imx6q-pcie 33800000.pcie: MEM 0x0018000000..0x001fefffff -> 0x0018000000
[ 3.346446] imx6q-pcie 33800000.pcie: iATU: unroll T, 4 ob, 4 ib, align 64K, limit 16G
[ 4.314182] imx6q-pcie 33800000.pcie: Phy link never came up
[ 4.320458] imx6q-pcie 33800000.pcie: PCI host bridge to bus 0000:00
[ 4.326885] pci_bus 0000:00: root bus resource [bus 00-ff]
[ 4.332426] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
[ 4.338644] pci_bus 0000:00: root bus resource [mem 0x18000000-0x1fefffff]
[ 4.345606] pci 0000:00:00.0: [16c3:abcd] type 01 class 0x060400 PCIe Root Port
[ 4.352978] pci 0000:00:00.0: BAR 0 [mem 0x00000000-0x000fffff]
[ 4.358942] pci 0000:00:00.0: ROM [mem 0x00000000-0x0000ffff pref]
[ 4.365177] pci 0000:00:00.0: PCI bridge to [bus 01-ff]
[ 4.370447] pci 0000:00:00.0: bridge window [io 0x0000-0x0fff]
[ 4.376576] pci 0000:00:00.0: bridge window [mem 0x00000000-0x000fffff]
[ 4.383400] pci 0000:00:00.0: bridge window [mem 0x00000000-0x000fffff pref]
[ 4.390714] pci 0000:00:00.0: supports D1
[ 4.394759] pci 0000:00:00.0: PME# supported from D0 D1 D3hot D3cold
[ 4.404627] pci 0000:00:00.0: BAR 0 [mem 0x18000000-0x180fffff]: assigned
[ 4.411485] pci 0000:00:00.0: ROM [mem 0x18100000-0x1810ffff pref]: assigned
[ 4.418582] pci 0000:00:00.0: PCI bridge to [bus 01-ff]
[ 4.423859] pci_bus 0000:00: resource 4 [io 0x0000-0xffff]
[ 4.429481] pci_bus 0000:00: resource 5 [mem 0x18000000-0x1fefffff]
[ 4.436366] pcieport 0000:00:00.0: PME: Signaling with IRQ 225

Running lspci only shows the Root Complex:
sh-5.2# lspci
00:00.0 Class 0604: 16c3:abcd
sh-5.2# lspci -nn
00:00.0 Class 0604: 16c3:abcd
sh-5.2# lspci -vvv
00:00.0 Class 0604: 16c3:abcd

My questions are:

How should PCIe be correctly connected and configured between i.MX8MP (RC) and an FPGA (EP)?
What device tree and kernel configuration settings are required on i.MX8MP for successful PCIe link training?
How can I verify PCIe link status (LTSSM state, link speed, width) on i.MX8MP?
Once the link is up, how can I ensure the FPGA endpoint is properly enumerated so that Vendor ID and Device ID are detected?

Any reference designs, FPGA PCIe EP configuration guidelines, or debugging steps would be greatly appreciated.

Thanks & Regards

Re: IMX8MP Board PCIe Phy link never came up

Hi,

How did you perform the test? Did you first boot the setup ep, then boot the rc? Or did you boot the rc first? Also, if the FPGA isn't connected, are there any logs related to “Phy link never came up”?

Best Regards,
Zhiming

Re: IMX8MP Board PCIe Phy link never came up

HI @Zhiming_Liu ,

Here is how the testing was performed and the current observations:

The PCIe reference clock (100 MHz) is sourced from the FPGA to the i.MX processor. This clock has been verified on the board using an oscilloscope and is stable.
After booting the processor, the i.MX is detected as a PCIe Root Complex and its RC ID is correctly assigned.
$lspci -nn
```
00:00.0 Class 0604: 16c3:abcd
```
Boot order was tested in both ways:
- Root Complex (i.MX) booted first, then the Endpoint (FPGA)
- Endpoint booted first, then the Root Complex
  The behavior was the same in both cases.
Currently, the PCIe link does not come up. Guidance is requested on how the PCIe link training should be established between the i.MX (RC) and the FPGA (EP).
Specifically:
- Which side initiates the link training (RC or EP)?
- What conditions must be met on the RC side for successful link-up?
- Does the i.MX Root Complex automatically start PCIe link training once the EP is present and reference clock/reset are valid?
- Are there any mandatory actions required on the FPGA side (for example, enabling LTSSM, or configuring PCIe IP) before the RC can detect the Endpoint?