Hello,
I'm planning a FlexSPI FPGA interface application for i.MX 93 and reviewing possible throughput. I'm using a module that provides SD3 for QSPI and SD1 for eMMC. Because DQS line is already occupied with eMMC interface, I'm restricted to clocking mode FlexSPIn_MCR0[RXCLKSRC] = 0x0 and 0x2 if I understand right. Although reference manual suggests "medium" speed similar to mode 0x1, there's no max frequency specification for mode 0x2 in datasheet.
Any reason why mode 0x2 has been omitted in datasheet? Can we expect speed similar to mode 0x1? I presume mode 0x1 can't be used if DQS pin is muxed to other usage?
Best regards
Frank
Hello @FvM
I hope you are doing very well.
You can find more information related to the FlexSPI interface in the table 195 of the Reference Manual.
Best regards,
Salas.
Hello @FvM
I asked internally.
Unfortunately, the RXCLKsrc=2 option was remove from the datasheet because characterization of the device revealed signal integrity issues on the loopback signal such that the behavior could not be guaranteed.
The mention of the option in the RM will be removed.
Best regards,
Salas.
Hello @Manuel_Salas,
thanks for answering.
I'm aware of FlexSPI reference manual section. My problem is that datasheet paragraph 4.12.9 FlexSPI timing parameters only specifies modes 0, 1 and 3 and doesn't even mention mode 2. Specifically I'm asking for mode 2 (SCK output and loopback from SCK pad) DDR timing parameters in nominal mode. Can we assume they are equal to mode 1?
I'm unable to use mode 1 or 3 because SD1_STROBE pin is occupied by eMMC interface in my application. Nevertheless I'm trying to achieve maximal throughput with QSPI FPGA interface.
Regards
Frank
Hello @Manuel_Salas,
many thanks for communicating the RXCLKsrc=2 issue openly. I understand our application is restricted to 66 MHz SDR/33 MHz DDR clock speed then, because it can't use DQS pin.
Best regards
Frank