2314063_en-US

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DDR4 calibration issues on LS1046 custom board

Good day!

We are trying to bring up our custom LS1046-based board up and stucked with DDR4 calibration procedure.

SPD data of the modules is red successfully, calibration process starts successfully too, but after that it fails with this reason(log from CodeWarrior

############################### Run 1

Result for: wrlvl_searcher

######################################

Test result: [

============================================================

Updated:

WRLVL_CNTL = 0x8655F605, WRLVL_CNTL_2 = 0x00000000,
WRLVL_CNTL_3 = 0x00000000, SDRAM_CLK_CNTL = 0x02800000

============================================================

Updated:

WRLVL_CNTL = 0x8655F60A, WRLVL_CNTL_2 = 0x0B0B0C0F,
WRLVL_CNTL_3 = 0x0F10110D, SDRAM_CLK_CNTL = 0x02800000

============================================================

Updated:

WRLVL_CNTL = 0x8655F60A, WRLVL_CNTL_2 = 0x0B0B0C0F,
WRLVL_CNTL_3 = 0x0F101115, SDRAM_CLK_CNTL = 0x02800000

============================================================

Updated:

WRLVL_CNTL = 0x8655F60A, WRLVL_CNTL_2 = 0x0B0B0C0F,
WRLVL_CNTL_3 = 0x0F10111D, SDRAM_CLK_CNTL = 0x02800000

Write Leveling start values are correct and require no further modification,
but the test failed due to other issues.

Most common failure causes:

-incorrect values configured in DDR4 DQn_MAP registers
-incorrect ODT values
-incorrect driver strength selected
-incorrect timing values selected for Timing Configuration 0 properties (TIMING_CFG_0 register)

<>

{{Write Leveling start values are correct and require no further modification,
but the test failed due to other issues.}}

Err. capture registers:

0xE20, 0xDEADBEEF
0xE24, 0xDEADBEEF
0xE28, 0x00000000
0xE40, 0x00000000
0xE44, 0x00000000
0xE48, 0x0000001D
0xE4C, 0x60FF2001
0xE50, 0x00001FC0
0xE54, 0x00000000
0xE58, 0x00010000

############################################

DQ mapping seems to be OK - we have 1:1 mapping from CPU to DDR slot, so we use DQ mappings from DDR module SPD without changing.

What can be the problem?

Re: DDR4 calibration issues on LS1046 custom board

Is there available RCW on the customer board?

Has the ASLEEP led turned on and off?

What's the frequency of the DDR clock?

Thanks

Re: DDR4 calibration issues on LS1046 custom board

DDR calibration is performed using a hardcoded RCW.

System clock - 100 MHz DDR bus clock - 800 MHz, DDR data rate - 1600 mt/s

Memory module - non-ECC.

One interesting thing - from timer to time the 1 st stage of calibration (wrtlvl search) is successfully passed.

For example:

Test result: [ =================================================

Updated:

WRLVL_CNTL = 0x8655F605, WRLVL_CNTL_2 = 0x00000000,

WRLVL_CNTL_3 = 0x00000000, SDRAM_CLK_CNTL = 0x02800000

============================================================

Updated:

WRLVL_CNTL = 0x8655F609, WRLVL_CNTL_2 = 0x0A0B0C0E,

WRLVL_CNTL_3 = 0x0F10110D, SDRAM_CLK_CNTL = 0x02800000

============================================================

Updated:

WRLVL_CNTL = 0x8655F609, WRLVL_CNTL_2 = 0x0A0B0C0E,

WRLVL_CNTL_3 = 0x0F101115, SDRAM_CLK_CNTL = 0x02800000

============================================================

Updated:

WRLVL_CNTL = 0x8655F609, WRLVL_CNTL_2 = 0x0A0B0C0F,

WRLVL_CNTL_3 = 0x0F10111D, SDRAM_CLK_CNTL = 0x02800000

<>

Err.capture registers:

0xE20, 0x00000000 0xE24, 0x00000000 0xE28,0x00000000

0xE40,0x00000000 0xE44,0x00000000 0xE48, 0x0000001D

0xE4C, 0x00000000 0xE50,0x00000000 0xE54,0x00000000

0xE58, 0x00010000

Dump:

0xF00,0x00000000 0xF04, 0x00000002 0xF08, 0x0000000F

0xF0C,0x14000C20 0xF10, 0x00000000 0xF14, 0x00000000

0xF18, 0x00000000 0xF1C, 0x00000000 0xF20, 0x00000000

0xF24, 0x2F003000 0xF28, 0x32003400 0xF2C, 0x39003B00

0xF30, 0x3C003E00 0xF34, 0x00005000 0xF38, 0x00000000

0xF3C, 0x00000000 0xF40, 0x00000000 0xF44, 0x00000000

0xF48, 0x00000001 0xF4C, 0xD4000000 0xF50, 0x13001500

0xF54, 0x17001900 0xF58, 0x1D001F00 0xF5C, 0x21002200

0xF60, 0x3A000000 0xF64, 0x00009000 0xF68, 0x00000020

0xF6C, 0x00000000 0xF70, 0x0070006F 0xF74, 0x00000000

0xF78, 0x00000000 0xF7C, 0x00000000 0xF80, 0x00000000

0xF84, 0x00000000 0xF88, 0x00000000 0xF8C, 0x00000000

0xF90, 0x00000000 0xF94, 0x80000000 0xF98, 0x00000000

0xF9C, 0x34043104 0xFA0, 0x35043304 0xFA4, 0x31043304

0xFA8, 0x2F043104 0xFAC, 0x04040000 0xFB0, 0x00000003

0xFB4, 0x1F1E1F21 0xFB8, 0x1E1C1F1D 0xFBC, 0x1F1B1D1E

0xFC0, 0x1C1B1C1C 0xFC4, 0x1F1E1F22 0xFC8, 0x1F1F2120

0xFCC, 0x1F1E1F20 0xFD0, 0x1C1D201F 0xFD4, 0x1F1B1B1E

0xFD8, 0x1F1D1E1C 0xFDC, 0x1F1F1D1F 0xFE0, 0x1F1D1E1C

0xFE4, 0x1F1C191A 0xFE8, 0x1C1D1C1A 0xFEC, 0x1F1E1C1E

0xFF0, 0x1E1F1E1A 0xFF4, 0x1F1F1F1F 0xFF8, 0x1F1F1F1F

0xFFC, 0x1F000000

Data:

0x00000009 0x0000000a 0x0000000b 0x0000000c 0x0000000f

0x0000000f 0x00000010 0x00000011 0x0000001d

Just after that I start calibration process again(without any changes in settings) and get a fail:

########## Result for: wrlvl_searcher ######

Test result: [

Updated: WRLVL_CNTL = 0x8655F605, WRLVL_CNTL_2 = 0x00000000,

WRLVL_CNTL_3 = 0x00000000, SDRAM_CLK_CNTL = 0x02800000

============================================================

Updated: WRLVL_CNTL = 0x8655F609, WRLVL_CNTL_2 = 0x0A0B0C0E,

WRLVL_CNTL_3 = 0x0F10110D, SDRAM_CLK_CNTL = 0x02800000

============================================================

Updated: WRLVL_CNTL = 0x8655F609, WRLVL_CNTL_2 = 0x0A0B0C0E,

WRLVL_CNTL_3 = 0x0F101115, SDRAM_CLK_CNTL = 0x02800000

============================================================

Updated: WRLVL_CNTL = 0x8655F609, WRLVL_CNTL_2 = 0x0A0B0C0E,

WRLVL_CNTL_3 = 0x0F10111D, SDRAM_CLK_CNTL = 0x02800000

Write Leveling start values are correct and require no further modification, but the test

failed due to other issues. Most common failure causes:

- incorrect values configured in DDR4 DQn_MAP registers

- incorrect ODT values

- incorrect driver strength selected

- incorrect timing values selected for Timing Configuration 0 properties (TIMING_CFG_0 register)

<>

{{Write Leveling start values are correct and require no further modification, but the test failed due to other issues.}}

Err. capture registers:

0xE20, 0xDEADBEEF 0xE24, 0xDEADBEEF 0xE28, 0x00000000 0xE40, 0x00000000

0xE44, 0x00000000 0xE48, 0x0000001D 0xE4C, 0x60FF2001 0xE50, 0x00001FC0

0xE54, 0x00000000 0xE58, 0x00010000

Dump:

0xF00, 0x00000000 0xF04, 0x00000002 0xF08, 0x0000000E 0xF0C, 0x14000C20

0xF10, 0x00000000 0xF14, 0x00000000 0xF18, 0x00000000 0xF1C, 0x00000000

0xF20, 0x00000000 0xF24, 0x2F003100 0xF28, 0x33003400 0xF2C, 0x3A003A00

0xF30, 0x3C003E00 0xF34, 0x00005000 0xF38, 0x00000000 0xF3C, 0x00000000

0xF40, 0x00000000 0xF44, 0x00000000 0xF48, 0x00000001 0xF4C, 0xD4000000

0xF50, 0x13001500 0xF54, 0x17001900 0xF58, 0x1D001F00 0xF5C, 0x21002200

0xF60, 0x3A000000 0xF64, 0x00009000 0xF68, 0x00000020 0xF6C, 0x00000000

0xF70, 0x0070006F 0xF74, 0x00000000 0xF78, 0x00000000 0xF7C, 0x00000000

0xF80, 0x00000000 0xF84, 0x00000000 0xF88, 0x00000000 0xF8C, 0x00000000

0xF90, 0x00000000 0xF94, 0x80000000 0xF98, 0x00000000 0xF9C, 0x31022F02

0xFA0, 0x33023102 0xFA4, 0x30023102 0xFA8, 0x2E022F02 0xFAC, 0x02020000

0xFB0, 0x10000003 0xFB4, 0x46444650 0xFB8, 0x45445142 0xFBC, 0x51445052

0xFC0, 0x46454544 0xFC4, 0x45434651 0xFC8, 0x44455045 0xFCC, 0x46455051

0xFD0, 0x45455146 0xFD4, 0x52505052 0xFD8, 0x52505246 0xFDC, 0x50464546

0xFE0, 0x51465042 0xFE4, 0x53464650 0xFE8, 0x52515145 0xFEC, 0x50454546

0xFF0, 0x45505142 0xFF4, 0x46464646 0xFF8, 0x52515350 0xFFC, 0x00000000

Data:

0x00000009 0x0000000a 0x0000000b 0x0000000c 0x0000000e 0x0000000f 0x00000010 0x00000011 0x00000025

########################################################

Also I' ve noticed that Lane 8 is probed during calibration process, despite to that fact that ddr module is non-ecc and ecc is disabled in project settings.

Re: DDR4 calibration issues on LS1046 custom board

1.The QCVS does not support hardcoded RCW official, valid RCW has to be presented in the RCW source flash or SD card.

Would you kindly program the RCW into the flash first, and then do the QCVS DDR validation.

2.Run the command below in the CCS:

(bin) 42 % delete all

(bin) 43 % config cc cwtap

(bin) 44 % show cc

(bin) 45 % ccs::config_chain {ls1043a dap sap2}

(bin) 46 % display ::ccs::get_config_chain

(bin) 47 % ccs::reset_to_debug

Send the logs to me.

3.would you kindly share the schematics and confirm the layout follow the

AN5097, Hardware and Layout Design Considerations for DDR4 SDRAM Memory Interfaces

Thanks

Re: DDR4 calibration issues on LS1046 custom board

The problem was solved by updating to new version of QCVS(4.27.0)