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[#1]

i.MX8M plus, single channel ddr on channel B

Is it possible to use a single channel lpddr4 16bit that is only connected on channel B with the i.MX8M plus?

We have a design where A is connected to B and B to A, will this design work if swapping to a single channel lpddr4?

i.MX 8M | i.MX 8M Mini | i.MX 8M NanoRe: i.MX8M plus, single channel ddr on channel B

Hi @johan_carlsson,

Thank you for contacting NXP Support!

Based in iMX8MP Hardware design guide, iMX8MP datasheet and iMX8MP Reference Manual.

No. NXP neither documents nor validates a single‑channel LPDDR4 (16‑bit) design connected only to Channel B on the i.MX 8M Plus. The single‑channel configuration assumed in the documentation and reference designs is on Channel A.

A design with A <-> B crossed (A wired to B and B wired to A) is not supported.

Best Regards,

Chavira

Re: i.MX8M plus, single channel ddr on channel B

HI Chavira, are you sure about this?

the TRM says this,

dav1_0-1770225981863.png

so shouldn't changing DqLnSel registers allow (per byte lane / slice) to be changed from A to B?

Re: i.MX8M plus, single channel ddr on channel B

Hi @dav1,

I noticed some misunderstanding here.

According to the Reference Manual:

"Supports mapping of PHY dq to DRAM dq within a byte (swizzle)… per‑dbyte… each register in a byte’s set of DqLnSel must have a unique value…”

This means the PHY lets you undo board level bit to bit scrambling inside a single 8‑bit slice (dbyte). For example, if PHY lane 3 routes to DRAM DQ0 within that same dbyte, you set Dq0LnSel = 3 for that dbyte. This helps things like MRR binary counters return correct values after the swizzle is logically undone.

Re: i.MX8M plus, single channel ddr on channel Bwould it be possible to do this workaround
- setup the DDR as 2 channels
- configure it so that it doesn't interleave across A and B
- define only the B section as validRe: i.MX8M plus, single channel ddr on channel B

HI @dav1,

At this time, this configuration has not been validated and is not expected to be possible.

While you may attempt to test it, please note that this is outside the intended functionality of the RAM PHY, and therefore reliable operation is not expected.

Best Regards,
Chavira

Re: i.MX8M plus, single channel ddr on channel B

If there is anything wrong with my reply, please point it out. If there isn’t any problem and this post gets deleted again like the previous times, then I will post this on Facebook.

But Why the RPA tool shows, it can do swap.

MX8M_Plus_LPDDR4_RPA_v10.xlsx
https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/i-MX-8MPlus-m865S-DDR-Register-Programmi...

3-1.png

1.png

2.png

Re: i.MX8M plus, single channel ddr on channel B

did you try it?

i.MX8M plus, single channel ddr on channel B.png

 

Re: i.MX8M plus, single channel ddr on channel B

@dav1 If a swap issue occurs, the table will turn red and show a warning. However, when Channel A and Channel B are swapped, this RPA tool still shows green, and the corresponding registers are also modified.

Therefore, there are only two possibilities:

The RPA tool is wrong.

The Reference Manual is wrong.

One of two must be true. This is what @Chavira  needs to clarify/answer.