2299373_en-US

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SEMC SRAM burst disable on i.MXRT1170

I am using SEMC with SRAM in asynchronous mode with 16b port width and non-multiplexed on RT1176. Is it possible to disable burst accesses completely? The slave is having problems with it, especially for write accesses.

What I mean is that I want CS to go high after every WRN/OE. Currently it looks like this:

Here we have a burst of 4 writes with four WRN in a single CS cycle.

In the past we used RT1064 with 16b port width and multiplexed and did not face such issues.

Here you see 3 writes, each with a dedicated CS cycle.

Thank you for your help.

i.MXRT 106x

Re: SEMC SRAM burst disable on i.MXRT1170

Hi @glaukos ,

Thank you so much for your interest in our products and for using our community.

I think the behavior you are observing (multiple writes under a single CS assertion) is mainly caused by the Arm Cortex‑M7 core, not by the SEMC controller itself.

When the SEMC memory region is configured as Normal memory in the MPU (Memory Protection Unit), the Cortex‑M7 core may buffer and merge consecutive write accesses.

I checked the RT1170 RM and didn’t find any SEMC register bit that can disable this burst behavior.

I suggest you can try to configure the SEMC SRAM region as Device memory in the MPU.

Wish it helps you

Best Regards

MayLiu

Re: SEMC SRAM burst disable on i.MXRT1170

Hi @mayliu1 ,

thank you for your help! I figured it out this morning, but the solution was a different one. I had a wrong value in the IOCR register, because bitfields there differ between RT1064 and RT1170 and I did not notice. What I thought was CS in my screenshot was actually another address line (A8). This worked on the lower address range where I was testing, where A8 was always low. With the correct value in the MUX_A8 field everything works as expected.