2260132_en-US

[#1]

RT1180 FlexIO and dual SPI (Master-Slave)

Hello, i've some issues to implement double SPI on the same FlexIO with no blocking function, it uses the same IRQ then it looks like somthing that set the busy flag for both SPI. 

if i open the connection between master and slave the master complete the transmission and jump in the call back correctly, but if i connect master and slave not works.

the same config with DMA works, i can attach the code, cabling is:

J41_12 - J41_8

J41_10 - J41_4

J69_15 -J41_2

switch to dma version is easy, set to 1

#define USING_DMA 1

FIFO version seti to 0

#define USING_DMA 0

if someone can help me to find the problem is very apprecieated

i.MXRTRe: RT1180 FlexIO and dual SPI (Master-Slave)

Thanks Edwin, you confirm my supposition. Than i'll works to optimize eDma function because is not usable if for example FLEXIO_SPI_SlaveTransferEDMA needs 37us and trasmission 10us. 

i was hopping to exist something that i didn't find in a reference manual or something hide form our "public eyes".

thanks again Edwin!

Simone

Re: RT1180 FlexIO and dual SPI (Master-Slave)

Hi @SimoneColomboWEG,

Although possible to construct two SPI instances on a single FlexIO module, these cannot be handled truly simultaneously (or in a non-blocking scheme) since both instances will report using the same IRQ vector and therefore share the same module status flags. This is why you see that both of the busy status flags get set, even if only one SPI is actually busy.

On the other hand, the implementation of DMA uses the DMA's own completion IRQs, which is why this implementation works.

My recommendation is to use the DMA, if you require having two SPI instances on a single FlexIO, as described on the AppNote of this exact implementation: Emulating Dual SPI Using FlexIO.

BR,
Edwin.