Hi Experts,
The customer is Hitachi, who has a question about I2C timing for the SE051C2. Hitachi plans to use the TI 66AK2G12. The 66AK2G12 complies with the popular I2C Bus specification.
https://www.nxp.com.cn/docs/en/user-guide/UM10204.pdf
However, the I2C bus timing for the SE051C2 requires an SDA hold time of at least 8 ns when low and at least 24 ns when high. https://www.nxp.com.cn/docs/en/data-sheet/SE051.pdf
Hitachi believes that this timing specification does not allow connection to a host device that complies with the general I2C bus specification.
How should we understand this?
Please kindly advise!
Best Regards,
Kan
Hello Kan,
this is only a limitation in case the host goes to the extreme border of I2C spec and updates SDA and SCL bus bits at the exact same time (with the risk of violating I2C bus specs which does not allow SDA to change before SCL). If a host goes to the extreme borders of I2C it risks that due to unsymmetries e.g. in the capacitance of the SDA and SCL the SDA line might actually change the signal level faster than SCL, although both got triggered at the same time.
Due to this risk usually all I2C bus hosts explicitly first update SCL, and only then update SDA, so forming typically a delay in the range of µs between the two signals to have enough margin to comply for sure with I2C spec even if the bus signal traces are not completely symmetric. Due to this there is usually no issue although the SE05x is here not 100% on the I2C bus spec.
Kind regards,
Michael