We are currently working with the i.MX RT1024 processor and plan to repurpose the BOOT_CFG[4] and BOOT_CFG[5] pins (corresponding to GPIO_EMC_22 and GPIO_EMC_23) for UART RX and TX functionality, in addition to their role in boot configuration.
To facilitate this dual-purpose usage, we have implemented a 6.2 ms delay circuit using the TPS3840DL30DBVRQ1 voltage supervisor and the SN74LVC1G125DCKR buffer. This setup is intended to control the enabling/disabling of the UART interface, ensuring that the boot configuration is correctly latched during power-up before the pins are repurposed for UART communication.
Given our requirement to use these pins for both boot configuration and UART, we would like to confirm whether this implementation is robust and reliable. Are there any recommended modifications or considerations to improve the design or ensure consistent behavior?
Hi @Ash7,
This delay circuit of 6.2ms should provide enough time for the RT1024 to finish its booting process while probing the BOOT_CFG pins without any interference of the UART.
Remember you could also spare this circuit by configuring the BOOT_CFG fuses instead of relying on the BOOT_CFG pins. But this is only recommended for production, and if the BOOT_CFG pins are meant to remain with the same values.
BR,
Edwin.