2163535_en-US

[#1]

S32R47 Clock Configuration Tool Issue

Topic: Clock Configuration Tool 

Customer: Internal

On copy: @rushikeshmunde 

Issue identified when trying to use the Clock Tool to configure the CSI2 module via COREPLL_PHI4. The S32R47_Clocking.xlsx sheet attached to the RM states that the max frequency of this clock is 100MHz however they get an error that says the maximum frequency must be between 0-40MHz.

Priority: MEDIUMS32_CONFIG_TOOLS32DSSource: Direct CustomerRe: S32R47 Clock Configuration Tool Issue

Hello Joe,

I can confirm that DDR_DFS1_CLK has the same error on my side. There is an error in C:\NXP\S32DS.3.6.1\eclipse\mcu_data\processors\S32R47\PlatformSDK_S32R4X\clocks\TOP.xml
 You should replace the 530 Mhz with 800.

<prescaler id="DDRPLL_DFS1" name="DDR_DFS1" description="DDR_DFS1. Expression used for division of input frequency value is 2*(DVPORT[MFI] + (DVPORT[MFN] / 36)).">

        <input signal="DDRPLL_VCO.clk"/>

        <divide expr="2 * (DDR_PLL_DFS::DVPORT0[MFI] + (DDR_PLL_DFS::DVPORT0[MFN] / 36.0))">

          <constraint cond_expr="DDR_PLL_DFS::DVPORT0[MFN] < 36" description="MFN should be smaller than 36"/>

          <constraint cond_expr="DDR_PLL_DFS::DVPORT0[MFI] > 0 && DDR_PLL_DFS::DVPORT0[MFI] < 256" when="DDR_DFS1_PD == `Power_up`" description="DFS value should be in [2:511]"/>

        divide>

        <enable cond_expr="DDR_PLL_DFS::CTL[DFS_RESET] == 0 && DDR_PLL_DFS::PORTRESET[RESET0] == 0" description="Periph DFS can be power up/down by using {{DDR_DFS1_PD}} settings.                                      In order to enable element, enter a division value(e.g. /2). Values can be integer or decimal."/>

        <constraint max_freq="530 MHz" when="DDRPLL_VCO.enable == `true` && DDRPLL_DFS1.enable == `true`"/>

I will update the RTD ticket to include this clock as well.

Please raise a new query next time even if it is related to this one. You can put a link to this post if needed.
Thank you,
Marius

Re: S32R47 Clock Configuration Tool Issue

Hi Marius,

I have just tried to configure the DDR_CLK using the clocks tool and I am running into another error. I have only just updated to the latest RTD update sites so I am curious to see if you can replicate this on your side or if it is a package issue on my side.

Based on the RM I should be able to configure DDR_CLK up to a maximum of 800MHz. When trying todo this using the Clocks Tool I am getting an error on the output of the DDR_DFS1 frequency that says:

"The output frequency must be lower than or equal to 530 MHz" (see attached image)

This is in contradiction of the maximum stated output of the DDR_DFS1_CLK which is 800MHz as per RM.

Re: S32R47 Clock Configuration Tool Issue

Hello @JDonnelly ,

I have created a JIRA ticket for RTD to solve this in the future release: https://jira.sw.nxp.com/browse/ARTD-203323
For now the client can manually change the following files with the respective numbers in order to unblock them:

C:\NXP\S32DS.3.6.1\eclipse\mcu_data\processors\S32R47\PlatformSDK_S32R4X\clocks\TOP.xml

       
        [DIV]+1"/>
        [DE] == 1" description="Core PLL Output Divider 4 can be enabled/disabled using CORE_PLLODIV_4_DE settings."/>
       

C:\NXP\S32DS.3.6.1\eclipse\mcu_data\processors\S32R47\PlatformSDK_S32R4X\clocks\MODULE_CLOCKS.xml

      [SELCTL] == 8"/>
...

      [SELCTL] == 8"/>

C:\NXP\S32DS.3.6.1\S32DS\software\PlatformSDK_S32R4X\RTD\Resource_TS_T40D95M8I0R0\resource\CORTEXM_S32R4X_s32r47_bga548.properties

MCU.SysClock.Limits.CSI_CFG_CLK.High:250000000

Once the new numbers are applied a restart of Design Studio should clear the error and be able to use the clocks at maximum frequency as the user manual says.

If you have any other questions please let me know.

--Marius

Re: S32R47 Clock Configuration Tool Issue

Hello @JDonnelly ,

I have reproduced the issue on my side as well and now we are investigating to see what causes this issue and even try to provide you a workaround until the fix is officially released.

I will come back with an answer as soon as possible.
--Marius

Re: S32R47 Clock Configuration Tool Issue

Closing this since there is nothing else the support team can do. The workaround was accepted and actual fix is tracked in JIRA ticket.