our customed board with LS1043AXN8QQB and 2GB DDR4 can't be poweron reset porperly.
HW arch: LS1043A 2GB DDR4(512MB x8bit), with eMMC bootmode. eMMC was flash with all boot image(uboot, kernel, ...).
Poweron reset was controlled by some logic gates to check some power status, RESET signals, which followed the RDB reference design, detail design, please refer to the attached circuit.
Failure: after poweron, the board can't poweron reset properly with random failrate. we can captured the PORESET_B、RESET_REQ_B、and HRESET_B with periodly pluse if poweron reset failed. we also can captured that, there's always have SDHC_CLK output from LS1043A to eMMC chip. as below,
and Zoom in the wave as below,
can find the HRESET_B is pull-HIGH by LS1043A after bootup, meas that the system already finished PLL lock action, and begin to stop driving HRESET_B, but failed in [PBL fetchs PBI command from SD card, PBI writes to CCSR space and programs OCRAM with SPL] operation, and then GPP jumps to the boot ROM at 0x0000_0000, because the ASLEEP with NOT be driver LOW according the boot process sequence as below,
if there any suggestions to debug and fix this issue? Thanks.
During the debugging phase, the RESET_REQ_B needs to be able to communicate with the PORESET to prevent the MPU to prevent the MPU from continuously reset CPU The
RESET For circuit design, please refer to AN5012, LS1043A Design Checklist - Application Note JTAG interface connection, Figure 18. and LS1043ARDB board.
Please find PORESET has gone low. PORESET is triggered. CPU cannot operate normally.
The control logic for PORESET_B does not refer to the RDB reference design which is controlled with a CPLD, but instead uses a watchdog as shown below, and a combination of the aforementioned logic lines for the power-up reset.
In the first power-on startup, after the system is powered on the TPS3828 this watchdog chip comes with an internal 200ms delay output to control the release of PORESET_B, through the aforementioned logic gate line, and power detection logic with the gate logic, the output of CPU_PORESET_B to the LS1043A processor to start the reset.
After entering uboot or system, you can control the watchdog chip by reset or reboot command, and finally control RESET_REQ_B to perform system soft reset reboot.
The existence of such a reset control may affect the normal power-up startup of the system. Currently, the analysis is suspected to be a failure of the LS1043A to enter the OCRAM for initialization after startup.
It seems the PORESET causes the POR repeated.
Please check which signal cause the PORESET change from high to low.
DDR part will not affect the POR in this step.
You could use Chinese to reply.
Add more information, the DDR4 chip we used on the board is MT40A512M8SA-062E IT, which is 3200MT/s version, and used the LS1043ARDB(LS2108) default setting in ddr_init.c. Is the DDR chip or DDR settings impact the system poweron reset during initialized DDR controller in OCRAM?
I encountered a similar problem, an intermittent fault (occurring only once out of thousands of reboots): the software freezes during the u-boot startup process. The fault message is: "Synchronous Abort" handler, esr 0x02000000. Disassembling the call details, I found it to be : initr_pci→pci_init→dm_pciauto_config_device (pci_auto.c:371)→dm_pci_hose_probe_bus (pci-uclass.c:607)→dm_pciauto_prescan_setup_bridge→bl dm_pci_get_bdf. When ret returns, an exception occurs at address 0x8202fc20. The problem lies in ret reaching an incorrect address, while the called esr is merely a register shift; it itself has no inherent error-prone aspects (no memory access, no jumps).
The software uses cpld to actively feed the watchdog (external watchdog), and the external watchdog is reset using PORESET, but it failed. Could you please advise on the problem?
I suggest starting a new topic for this question, thank you.
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