Hi.
When CCM_ANALOG_PLL_DDR is set to 0x0000302C, DRAM_SDCLK0 is 132MHz.
So when the TEST_DIV_SELECT bit of CCM_ANALOG_PLL_DDR is set to 0x01 and set to 0x0020302C, DRAM_SDCLK0 is about 270MHz.
It is half of 533Mhz.
DRAM_PHYM_ALT_CLK_ROOT and DRAM_ALT_CLK_ROOT are set to DDR_PLL_DIV2.
Is there a setting to set it to 1/2?
Best regards.
Hi Joanxie.
Thank you.
There is a 1/2 difference between the calculated result and the actual DDR_SDCKE.
I don't know why, but I'll end it here for now.
As the frequency increases, the voltage level of DDR_SDCLKE decreases.
So I think about lowering the frequency.
Best regards.
the driver I showed just tell you the formula, you need read the register CCM_ANALOG_PLL_DDR, CCM_ANALOG_PLL_DDR_NUM and CCM_ANALOG_PLL_DDR_DENOM, to check if they are correct
Hi Joanxie.
I'm building uboot-2022.01.
The code you showed is get_ddrc_clk(void).
What I found in this code
reg = readl(&ccm_reg->root[DRAM_CLK_ROOT].target_root;
DRAM_CLK_ROOT, which is not written in "Fugure 5-7.DRAM_Clock Structure", is loaded into reg.
The initial value of DRAM_CLK_ROOT was 0x00000001.
Clearing DRAM_CLK_ROOT made it display correctly.
However, DRAM_SDCKE0 is 270MHz. Is this correct? I checked it with an oscilloscope.
Best regards.
I checked the source code as below
https://github.com/nxp-imx/uboot-imx/blob/lf_v2025.04/arch/arm/mach-imx/mx7/clock.c#L162
checked the function decode_pll
case PLL_DDR:
reg = readl(&ccm_anatop->pll_ddr);
if (reg & CCM_ANALOG_PLL_DDR_POWERDOWN_MASK)
return 0;
num = ccm_anatop->pll_ddr_num;
denom = ccm_anatop->pll_ddr_denom;
if (reg & CCM_ANALOG_PLL_DDR_BYPASS_MASK)
return MXC_HCLK;
div_sel = (reg & CCM_ANALOG_PLL_DDR_DIV_SELECT_MASK) >>
CCM_ANALOG_PLL_DDR_DIV_SELECT_SHIFT;
return infreq * (div_sel + num / denom);
so the formula is 24M*(DIV_SELECT+(NUM/DENOM)), div_sel is from CCM_ANALOG_PLL_DDR, mum is from CCM_ANALOG_PLL_DDR_NUM) and denom is from CCM_ANALOG_PLL_DDR_DENOM
Hi Joanxie.
I understand the diagram you explained.
However, the reference manual does not explain which register FASTMIX is.
Please tell me the register name.
In this case, should TEST_DIV_SELECT of CCM_ANALOG_PLL_DDRn be set to 0x00?
Best regards.
Is there a setting to set it to 1/2?
>what do you mean? do you mean you need 533Mhz for
refer to the figure 5-7, The dedicate DRAM_PLL is used to generate 2x clock at 1066MHz, and use a divider to divide it by 2 to get 533MHz clock with good duty cycle. This 533MHz clock will be
used as the PHY_MCLK. Meanwhile, the 1066MHz clock will also be divided by 2 with
the 1/N divider to get 533MHz as the PHY_CLK, there is a 1/N divider used to divide the PHY clockdown to lower frequency such as 266MHz or 133MHz. The 1/N divider is a 3-bit divider
so N can be 2 to 8. so just set this 1/N to 1/2, you can get 533Mhz