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2146693_en-US
2146693_en-US
Hi Teams,
Customer: Quanta
Platform: S32G3
Module: FreeRTOS SMP support
The Quanta is investing example of FreeRTOS v11 with SMP support in our FreeRTOS_4_0_3_CD3 package and they would like to know implementation details of SMP support on the S32G3 Cortex-M7 platform.
1. How SMP is enabled and managed on the Cortex-M7 cores of the S32G3;
2. What is the actual extent of SMP support (e.g., task scheduling, synchronization, inter-core communication);
3. Whether cache coherence is supported by hardware, or if the implementation requires disabling caches entirely.
Thanks for your support in advance.
Best Regards,
Leo
Thanks for your support. I will feedback these answer to customer.
BR,
Leo
Hi @LeoLiAP I shall mark this information is solution for your question. If any unclear, please feedback and I shall unmark it.
Hi @LeoLiAP ,
1. With release 4.0.3 CD3, we’ve included the S32DS sample FreeRTOS_SMP_Example_S32G399, which provides built-in support for SMP. No additional configuration is required to enable SMP, enabling and managing SMP done on S32DS configuration, it's ready to use.
2. S32G SMP shall be supported APIs task scheduler, Queue and Semaphore.
For inter-core communication, used inter-core interrupts for signaling between cores, triggering rescheduling cores, haven't yet supported Stream Buffer, Msg Buffer APIs.
The remaining APIs that are not mentioned above, we have not tested yet, not ensure working.
3. S32G SMP can work when enabling cache.
Not support with FPU enabled.
You're welcome to bring up any questions.
Best Regards,
Cong